2022-08-02 08:03:50 +00:00
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/*
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* Copyright (C) 2021 Intel Corporation. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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*/
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/**
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* @file jit-ir.def
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*
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* @brief Definition of JIT IR instructions and annotations.
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*/
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/**
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* @def INSN (NAME, OPND_KIND, OPND_NUM, FIRST_USE)
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*
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* Definition of IR instructions
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*
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* @param NAME name of the opcode
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* @param OPND_KIND kind of the operand(s)
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* @param OPND_NUM number of the operand(s)
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* @param FIRST_USE index of the first use register
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*
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* @p OPND_KIND and @p OPND_NUM together determine the format of an
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* instruction. There are four kinds of formats:
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*
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* 1) Reg: fixed-number register operands, @p OPND_NUM specifies the
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* number of operands;
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*
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* 2) VReg: variable-number register operands, @p OPND_NUM specifies
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* the number of fixed register operands;
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*
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* 3) TableSwitch: tableswitch instruction's format, @p OPND_NUM must
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* be 1;
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*
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* 4) LookupSwitch: lookupswitch instruction's format, @p OPND_NUM
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* must be 1.
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*
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* Instruction operands are all registers and they are organized in an
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* order that all registers defined by the instruction, if any, appear
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* before the registers used by the instruction. The @p FIRST_USE is
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* the index of the first use register in the register vector sorted
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* in this order. Use @c jit_insn_opnd_regs to get the register
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* vector in this order and use @c jit_insn_opnd_first_use to get the
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* index of the first use register.
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*
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* Every instruction with name @p NAME has the following definitions:
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*
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* @c JEFF_OP_NAME: the enum opcode of insn NAME
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* @c jit_insn_new_NAME (...): creates a new instance of insn NAME
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*
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* An instruction is deleted by function:
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*
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* @c jit_insn_delete (@p insn)
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*
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* In the scope of this IR's terminology, operand and argument have
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* different meanings. The operand is a general notation, which
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* denotes every raw operand of an instruction, while the argument
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* only denotes the variable part of operands of instructions of VReg
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* kind. For example, a VReg instruction phi node "r0 = phi(r1, r2)"
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* has three operands opnd[0]: r0, opnd[1]: r1 and opnd[2]: r2, but
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* only two arguments arg[0]: r1 and arg[1]: r2. Operands or
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* arguments of instructions with various formats can be access
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* through the following APIs:
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*
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* @c jit_insn_opnd (@p insn, @p n): for Reg_N formats
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* @c jit_insn_opndv (@p insn, @p n): for VReg_N formats
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* @c jit_insn_opndv_num (@p insn): for VReg_N formats
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* @c jit_insn_opndts (@p insn): for TableSwitch_1 format
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* @c jit_insn_opndls (@p insn): for LookupSwitch_1 format
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*/
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#ifndef INSN
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#define INSN(NAME, OPND_KIND, OPND_NUM, FIRST_USE)
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#endif
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/* Move and conversion instructions that transfer values among
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registers of the same kind (move) or different kinds (convert) */
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INSN(MOV, Reg, 2, 1)
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INSN(PHI, VReg, 1, 1)
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/* conversion. will extend or truncate */
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INSN(I8TOI32, Reg, 2, 1)
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INSN(I8TOI64, Reg, 2, 1)
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INSN(I16TOI32, Reg, 2, 1)
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INSN(I16TOI64, Reg, 2, 1)
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INSN(I32TOI8, Reg, 2, 1)
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INSN(I32TOU8, Reg, 2, 1)
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INSN(I32TOI16, Reg, 2, 1)
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INSN(I32TOU16, Reg, 2, 1)
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INSN(I32TOI64, Reg, 2, 1)
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INSN(I32TOF32, Reg, 2, 1)
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INSN(I32TOF64, Reg, 2, 1)
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INSN(U32TOI64, Reg, 2, 1)
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INSN(U32TOF32, Reg, 2, 1)
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INSN(U32TOF64, Reg, 2, 1)
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INSN(I64TOI8, Reg, 2, 1)
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INSN(I64TOI16, Reg, 2, 1)
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INSN(I64TOI32, Reg, 2, 1)
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INSN(I64TOF32, Reg, 2, 1)
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INSN(I64TOF64, Reg, 2, 1)
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INSN(F32TOI32, Reg, 2, 1)
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INSN(F32TOI64, Reg, 2, 1)
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INSN(F32TOF64, Reg, 2, 1)
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INSN(F32TOU32, Reg, 2, 1)
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INSN(F64TOI32, Reg, 2, 1)
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INSN(F64TOI64, Reg, 2, 1)
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INSN(F64TOF32, Reg, 2, 1)
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INSN(F64TOU32, Reg, 2, 1)
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/**
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* Re-interpret binary presentations:
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* *(i32 *)&f32, *(i64 *)&f64, *(f32 *)&i32, *(f64 *)&i64
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*/
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INSN(I32CASTF32, Reg, 2, 1)
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INSN(I64CASTF64, Reg, 2, 1)
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INSN(F32CASTI32, Reg, 2, 1)
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INSN(F64CASTI64, Reg, 2, 1)
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/* Arithmetic and bitwise instructions: */
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INSN(NEG, Reg, 2, 1)
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INSN(NOT, Reg, 2, 1)
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INSN(ADD, Reg, 3, 1)
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INSN(SUB, Reg, 3, 1)
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INSN(MUL, Reg, 3, 1)
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INSN(DIV_S, Reg, 3, 1)
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INSN(REM_S, Reg, 3, 1)
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INSN(DIV_U, Reg, 3, 1)
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INSN(REM_U, Reg, 3, 1)
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INSN(SHL, Reg, 3, 1)
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INSN(SHRS, Reg, 3, 1)
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INSN(SHRU, Reg, 3, 1)
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INSN(ROTL, Reg, 3, 1)
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INSN(ROTR, Reg, 3, 1)
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INSN(OR, Reg, 3, 1)
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INSN(XOR, Reg, 3, 1)
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INSN(AND, Reg, 3, 1)
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INSN(CMP, Reg, 3, 1)
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INSN(MAX, Reg, 3, 1)
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INSN(MIN, Reg, 3, 1)
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INSN(CLZ, Reg, 2, 1)
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INSN(CTZ, Reg, 2, 1)
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INSN(POPCNT, Reg, 2, 1)
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/* Select instruction: */
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INSN(SELECTEQ, Reg, 4, 1)
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INSN(SELECTNE, Reg, 4, 1)
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INSN(SELECTGTS, Reg, 4, 1)
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INSN(SELECTGES, Reg, 4, 1)
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INSN(SELECTLTS, Reg, 4, 1)
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INSN(SELECTLES, Reg, 4, 1)
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INSN(SELECTGTU, Reg, 4, 1)
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INSN(SELECTGEU, Reg, 4, 1)
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INSN(SELECTLTU, Reg, 4, 1)
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INSN(SELECTLEU, Reg, 4, 1)
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/* Memory access instructions: */
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INSN(LDEXECENV, Reg, 1, 1)
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INSN(LDJITINFO, Reg, 1, 1)
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INSN(LDI8, Reg, 3, 1)
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INSN(LDU8, Reg, 3, 1)
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INSN(LDI16, Reg, 3, 1)
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INSN(LDU16, Reg, 3, 1)
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INSN(LDI32, Reg, 3, 1)
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INSN(LDU32, Reg, 3, 1)
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INSN(LDI64, Reg, 3, 1)
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INSN(LDU64, Reg, 3, 1)
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INSN(LDF32, Reg, 3, 1)
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INSN(LDF64, Reg, 3, 1)
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INSN(LDPTR, Reg, 3, 1)
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INSN(LDV64, Reg, 3, 1)
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INSN(LDV128, Reg, 3, 1)
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INSN(LDV256, Reg, 3, 1)
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INSN(STI8, Reg, 3, 0)
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INSN(STI16, Reg, 3, 0)
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INSN(STI32, Reg, 3, 0)
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INSN(STI64, Reg, 3, 0)
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INSN(STF32, Reg, 3, 0)
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INSN(STF64, Reg, 3, 0)
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INSN(STPTR, Reg, 3, 0)
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INSN(STV64, Reg, 3, 1)
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INSN(STV128, Reg, 3, 1)
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INSN(STV256, Reg, 3, 1)
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/* Control instructions */
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INSN(JMP, Reg, 1, 0)
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INSN(BEQ, Reg, 3, 0)
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INSN(BNE, Reg, 3, 0)
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INSN(BGTS, Reg, 3, 0)
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INSN(BGES, Reg, 3, 0)
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INSN(BLTS, Reg, 3, 0)
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INSN(BLES, Reg, 3, 0)
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INSN(BGTU, Reg, 3, 0)
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INSN(BGEU, Reg, 3, 0)
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INSN(BLTU, Reg, 3, 0)
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INSN(BLEU, Reg, 3, 0)
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INSN(LOOKUPSWITCH, LookupSwitch, 1, 0)
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/* Call and return instructions */
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INSN(CALLNATIVE, VReg, 2, 1)
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2022-12-19 03:24:46 +00:00
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INSN(CALLBC, Reg, 4, 2)
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2022-08-02 08:03:50 +00:00
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INSN(RETURNBC, Reg, 3, 0)
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INSN(RETURN, Reg, 1, 0)
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2023-04-20 02:09:34 +00:00
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#if WASM_ENABLE_SHARED_MEMORY != 0
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/* Atomic Memory Accesses */
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/* op1(replacement val) op2(expected val) op3(mem data) op4(offset)
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* and in x86, the result is stored in register al/ax/eax/rax */
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INSN(AT_CMPXCHGU8, Reg, 4, 0)
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INSN(AT_CMPXCHGU16, Reg, 4, 0)
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INSN(AT_CMPXCHGI32, Reg, 4, 0)
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INSN(AT_CMPXCHGU32, Reg, 4, 0)
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INSN(AT_CMPXCHGI64, Reg, 4, 0)
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/* rmw operations:
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* op1(read value) op2(operand value) op3(mem data) op4(offset) */
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INSN(AT_ADDU8, Reg, 4, 1)
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INSN(AT_ADDU16, Reg, 4, 1)
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INSN(AT_ADDI32, Reg, 4, 1)
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INSN(AT_ADDU32, Reg, 4, 1)
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INSN(AT_ADDI64, Reg, 4, 1)
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INSN(AT_SUBU8, Reg, 4, 1)
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INSN(AT_SUBU16, Reg, 4, 1)
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INSN(AT_SUBI32, Reg, 4, 1)
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INSN(AT_SUBU32, Reg, 4, 1)
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INSN(AT_SUBI64, Reg, 4, 1)
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INSN(AT_ANDU8, Reg, 4, 1)
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INSN(AT_ANDU16, Reg, 4, 1)
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INSN(AT_ANDI32, Reg, 4, 1)
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INSN(AT_ANDU32, Reg, 4, 1)
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INSN(AT_ANDI64, Reg, 4, 1)
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INSN(AT_ORU8, Reg, 4, 1)
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INSN(AT_ORU16, Reg, 4, 1)
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INSN(AT_ORI32, Reg, 4, 1)
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INSN(AT_ORU32, Reg, 4, 1)
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INSN(AT_ORI64, Reg, 4, 1)
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INSN(AT_XORU8, Reg, 4, 1)
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INSN(AT_XORU16, Reg, 4, 1)
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INSN(AT_XORI32, Reg, 4, 1)
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INSN(AT_XORU32, Reg, 4, 1)
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INSN(AT_XORI64, Reg, 4, 1)
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INSN(AT_XCHGU8, Reg, 4, 1)
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INSN(AT_XCHGU16, Reg, 4, 1)
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INSN(AT_XCHGI32, Reg, 4, 1)
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INSN(AT_XCHGU32, Reg, 4, 1)
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INSN(AT_XCHGI64, Reg, 4, 1)
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INSN(FENCE, Reg, 0, 0)
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#endif
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2022-08-02 08:03:50 +00:00
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#undef INSN
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/**
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* @def ANN_LABEL (TYPE, NAME)
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*
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* Definition of label annotations.
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*
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* @param TYPE type of the annotation
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* @param NAME name of the annotation
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*
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* Each defined annotation with name NAME has the following APIs:
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*
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* @c jit_annl_NAME (cc, label): accesses the annotation NAME of
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* label @p label
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* @c jit_annl_enable_NAME (cc): enables the annotation NAME
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* @c jit_annl_disable_NAME (cc): disables the annotation NAME
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* @c jit_annl_is_enabled_NAME (cc): check whether the annotation NAME
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* is enabled
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*/
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#ifndef ANN_LABEL
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#define ANN_LABEL(TYPE, NAME)
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#endif
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/* Basic Block of a label. */
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ANN_LABEL(JitBasicBlock *, basic_block)
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/* Predecessor number of the block that is only used in
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jit_cc_update_cfg for updating the CFG. */
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ANN_LABEL(uint16, pred_num)
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/* Execution frequency of a block. We can split critical edges with
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empty blocks so we don't need to store frequencies of edges. */
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ANN_LABEL(uint16, freq)
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/* Begin bytecode instruction pointer of the block. */
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ANN_LABEL(uint8 *, begin_bcip)
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/* End bytecode instruction pointer of the block. */
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ANN_LABEL(uint8 *, end_bcip)
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/* Stack pointer offset at the end of the block. */
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ANN_LABEL(uint16, end_sp)
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/* The label of the next physically adjacent block. */
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ANN_LABEL(JitReg, next_label)
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/* Compiled code address of the block. */
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ANN_LABEL(void *, jitted_addr)
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#undef ANN_LABEL
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/**
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* @def ANN_INSN (TYPE, NAME)
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*
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* Definition of instruction annotations.
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*
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* @param TYPE type of the annotation
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* @param NAME name of the annotation
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*
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* Each defined annotation with name NAME has the following APIs:
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*
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* @c jit_anni_NAME (cc, insn): accesses the annotation NAME of
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* instruction @p insn
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* @c jit_anni_enable_NAME (cc): enables the annotation NAME
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* @c jit_anni_disable_NAME (cc): disables the annotation NAME
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* @c jit_anni_is_enabled_NAME (cc): check whether the annotation NAME
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* is enabled
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*/
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#ifndef ANN_INSN
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#define ANN_INSN(TYPE, NAME)
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#endif
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/* A private annotation for linking instructions with the same hash
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value, which is only used by the compilation context's hash table
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of instructions. */
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ANN_INSN(JitInsn *, _hash_link)
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#undef ANN_INSN
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/**
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* @def ANN_REG (TYPE, NAME)
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*
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|
* Definition of register annotations.
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*
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|
* @param TYPE type of the annotation
|
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|
|
* @param NAME name of the annotation
|
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|
*
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|
* Each defined annotation with name NAME has the following APIs:
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*
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|
* @c jit_annr_NAME (cc, reg): accesses the annotation NAME of
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* register @p reg
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* @c jit_annr_enable_NAME (cc): enables the annotation NAME
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* @c jit_annr_disable_NAME (cc): disables the annotation NAME
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* @c jit_annr_is_enabled_NAME (cc): check whether the annotation NAME
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* is enabled
|
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|
*/
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|
#ifndef ANN_REG
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|
#define ANN_REG(TYPE, NAME)
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#endif
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/* Defining instruction of registers satisfying SSA property. */
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|
ANN_REG(JitInsn *, def_insn)
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|
#undef ANN_REG
|
