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Fix fast jit issues (#1223)

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Fix br if not clear_value issue
Fix i64.DIV/REM issue: i64 result rax/rdx may be overwritten by following i32 load eax/edx
This commit is contained in:
Wenyong Huang 2022-06-14 07:28:53 +08:00 committed by GitHub
parent b84f11724b
commit 0ab070af96
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 29 additions and 10 deletions
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1
core/iwasm/fast-jit/fe/jit_emit_control.c
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@ -899,6 +899,7 @@ jit_compile_op_br_if(JitCompContext *cc, uint32 br_depth, uint8 **p_frame_ip)
SET_BUILDER_POS(if_basic_block); SET_BUILDER_POS(if_basic_block);
SET_BB_BEGIN_BCIP(if_basic_block, *p_frame_ip - 1); SET_BB_BEGIN_BCIP(if_basic_block, *p_frame_ip - 1);
clear_values(cc->jit_frame);
if (!handle_op_br(cc, br_depth, p_frame_ip)) if (!handle_op_br(cc, br_depth, p_frame_ip))
goto fail; goto fail;

38
core/iwasm/fast-jit/fe/jit_emit_numberic.c
View File

@ -512,7 +512,7 @@ compile_int_div_no_check(JitCompContext *cc, IntArithmetic arith_op,
case INT_DIV_S: case INT_DIV_S:
case INT_DIV_U: case INT_DIV_U:
{ {
JitInsn *insn = NULL; JitInsn *insn = NULL, *insn1 = NULL;
if (is_i32) { if (is_i32) {
GEN_INSN(MOV, eax_hreg, left); GEN_INSN(MOV, eax_hreg, left);
@ -520,8 +520,6 @@ compile_int_div_no_check(JitCompContext *cc, IntArithmetic arith_op,
insn = GEN_INSN(DIV_S, eax_hreg, eax_hreg, right); insn = GEN_INSN(DIV_S, eax_hreg, eax_hreg, right);
else else
insn = GEN_INSN(DIV_U, eax_hreg, eax_hreg, right); insn = GEN_INSN(DIV_U, eax_hreg, eax_hreg, right);
res = eax_hreg;
} }
else { else {
GEN_INSN(MOV, rax_hreg, left); GEN_INSN(MOV, rax_hreg, left);
@ -529,18 +527,29 @@ compile_int_div_no_check(JitCompContext *cc, IntArithmetic arith_op,
insn = GEN_INSN(DIV_S, rax_hreg, rax_hreg, right); insn = GEN_INSN(DIV_S, rax_hreg, rax_hreg, right);
else else
insn = GEN_INSN(DIV_U, rax_hreg, rax_hreg, right); insn = GEN_INSN(DIV_U, rax_hreg, rax_hreg, right);
res = rax_hreg;
} }
jit_lock_reg_in_insn(cc, insn, eax_hreg); jit_lock_reg_in_insn(cc, insn, eax_hreg);
jit_lock_reg_in_insn(cc, insn, edx_hreg); jit_lock_reg_in_insn(cc, insn, edx_hreg);
if (is_i32) {
res = jit_cc_new_reg_I32(cc);
insn1 = jit_insn_new_MOV(res, eax_hreg);
}
else {
res = jit_cc_new_reg_I64(cc);
insn1 = jit_insn_new_MOV(res, rax_hreg);
}
if (insn && insn1) {
jit_insn_insert_after(insn, insn1);
}
break; break;
} }
case INT_REM_S: case INT_REM_S:
case INT_REM_U: case INT_REM_U:
{ {
JitInsn *insn = NULL; JitInsn *insn = NULL, *insn1 = NULL;
if (is_i32) { if (is_i32) {
GEN_INSN(MOV, eax_hreg, left); GEN_INSN(MOV, eax_hreg, left);
@ -548,8 +557,6 @@ compile_int_div_no_check(JitCompContext *cc, IntArithmetic arith_op,
insn = GEN_INSN(REM_S, edx_hreg, eax_hreg, right); insn = GEN_INSN(REM_S, edx_hreg, eax_hreg, right);
else else
insn = GEN_INSN(REM_U, edx_hreg, eax_hreg, right); insn = GEN_INSN(REM_U, edx_hreg, eax_hreg, right);
res = edx_hreg;
} }
else { else {
GEN_INSN(MOV, rax_hreg, left); GEN_INSN(MOV, rax_hreg, left);
@ -557,12 +564,23 @@ compile_int_div_no_check(JitCompContext *cc, IntArithmetic arith_op,
insn = GEN_INSN(REM_S, rdx_hreg, rax_hreg, right); insn = GEN_INSN(REM_S, rdx_hreg, rax_hreg, right);
else else
insn = GEN_INSN(REM_U, rdx_hreg, rax_hreg, right); insn = GEN_INSN(REM_U, rdx_hreg, rax_hreg, right);
res = rdx_hreg;
} }
jit_lock_reg_in_insn(cc, insn, eax_hreg); jit_lock_reg_in_insn(cc, insn, eax_hreg);
jit_lock_reg_in_insn(cc, insn, edx_hreg); jit_lock_reg_in_insn(cc, insn, edx_hreg);
if (is_i32) {
res = jit_cc_new_reg_I32(cc);
insn1 = jit_insn_new_MOV(res, edx_hreg);
}
else {
res = jit_cc_new_reg_I64(cc);
insn1 = jit_insn_new_MOV(res, rdx_hreg);
}
if (insn && insn1) {
jit_insn_insert_after(insn, insn1);
}
break; break;
} }
#else #else