mirror of
https://github.com/bytecodealliance/wasm-micro-runtime.git
synced 2025-02-06 06:55:07 +00:00
Enable spectest on riscv64 (#2843)
Fix relocation issues on riscv and update test scripts and CI to enable test spec cases on riscv QEMU.
This commit is contained in:
Huang Qi
GitHub
parent
157c289d07
commit
453a29a9d4
17
.github/workflows/spec_test_on_nuttx.yml
vendored
17
.github/workflows/spec_test_on_nuttx.yml
vendored
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@ -59,11 +59,11 @@ jobs:
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# target: "riscv32_ilp32d",
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# use_fpu: true
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# },
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# {
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# config: "boards/risc-v/qemu-rv/rv-virt/configs/nsh64",
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# target: "riscv64",
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# use_fpu: false
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# },
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{
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config: "boards/risc-v/qemu-rv/rv-virt/configs/nsh64",
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target: "riscv64",
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use_fpu: false
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},
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]
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wamr_test_option: [
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@ -85,6 +85,11 @@ jobs:
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},
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]
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exclude:
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# XIP is not fully supported yet on RISCV64, some relocations can not be resolved
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- target_config: { config: "boards/risc-v/qemu-rv/rv-virt/configs/nsh64" }
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wamr_test_option: { mode: "-t aot -X" }
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steps:
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- name: Install Utilities
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run: |
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@ -160,7 +165,7 @@ jobs:
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find nuttx/boards -name defconfig | xargs sed -i '$a\${{ matrix.wamr_test_option.option }}'
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- name: Disable FPU for NuttX
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if: matrix.target_config.use_fpu== false
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if: matrix.target_config.use_fpu == false
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run: |
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find nuttx/boards -name defconfig | xargs sed -i '$a\# CONFIG_ARCH_FPU is not set\n'
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@ -11,6 +11,7 @@
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#define R_RISCV_CALL_PLT 19
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#define R_RISCV_PCREL_HI20 23
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#define R_RISCV_PCREL_LO12_I 24
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#define R_RISCV_PCREL_LO12_S 25
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#define R_RISCV_HI20 26
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#define R_RISCV_LO12_I 27
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#define R_RISCV_LO12_S 28
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@ -101,20 +102,20 @@ static SymbolMap target_sym_map[] = {
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REG_SYM(__truncdfsf2),
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REG_SYM(__unorddf2),
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REG_SYM(__unordsf2),
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#if __riscv_xlen == 32
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REG_SYM(__mulsf3),
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REG_SYM(__floatundidf),
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REG_SYM(__fixdfdi),
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REG_SYM(__floatsidf),
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REG_SYM(__floatunsidf),
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#if __riscv_xlen == 32
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REG_SYM(__fixdfsi),
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REG_SYM(__fixsfdi),
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REG_SYM(__fixsfsi),
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REG_SYM(__floatdidf),
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REG_SYM(__floatdisf),
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REG_SYM(__floatsidf),
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REG_SYM(__floatsisf),
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REG_SYM(__floatundidf),
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REG_SYM(__floatundisf),
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REG_SYM(__floatunsidf),
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REG_SYM(__floatunsisf),
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REG_SYM(__mulsf3),
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REG_SYM(__mulsi3),
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#endif
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#endif
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@ -269,9 +270,10 @@ typedef struct RelocTypeStrMap {
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}
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static RelocTypeStrMap reloc_type_str_maps[] = {
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RELOC_TYPE_MAP(R_RISCV_32), RELOC_TYPE_MAP(R_RISCV_CALL),
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RELOC_TYPE_MAP(R_RISCV_CALL_PLT), RELOC_TYPE_MAP(R_RISCV_PCREL_HI20),
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RELOC_TYPE_MAP(R_RISCV_PCREL_LO12_I), RELOC_TYPE_MAP(R_RISCV_HI20),
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RELOC_TYPE_MAP(R_RISCV_32), RELOC_TYPE_MAP(R_RISCV_64),
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RELOC_TYPE_MAP(R_RISCV_CALL), RELOC_TYPE_MAP(R_RISCV_CALL_PLT),
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RELOC_TYPE_MAP(R_RISCV_PCREL_HI20), RELOC_TYPE_MAP(R_RISCV_PCREL_LO12_I),
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RELOC_TYPE_MAP(R_RISCV_PCREL_LO12_S), RELOC_TYPE_MAP(R_RISCV_HI20),
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RELOC_TYPE_MAP(R_RISCV_LO12_I), RELOC_TYPE_MAP(R_RISCV_LO12_S),
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};
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@ -327,21 +329,37 @@ apply_relocation(AOTModule *module, uint8 *target_section_addr,
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rv_set_val((uint16 *)addr, val_32);
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break;
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}
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#if __riscv_xlen == 64
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case R_RISCV_64:
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{
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uint64 val_64 =
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(uint64)((uintptr_t)symbol_addr + (intptr_t)reloc_addend);
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(uint64)((intptr_t)symbol_addr + (intptr_t)reloc_addend);
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CHECK_RELOC_OFFSET(sizeof(uint64));
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if (val_64
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!= (uint64)((intptr_t)symbol_addr + (intptr_t)reloc_addend)) {
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goto fail_addr_out_of_range;
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}
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bh_memcpy_s(addr, 8, &val_64, 8);
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#ifdef __riscv_zifencei
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__asm__ volatile("fence.i");
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#else
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__asm__ volatile("fence");
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#endif
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break;
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}
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#endif
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case R_RISCV_CALL:
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case R_RISCV_CALL_PLT:
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case R_RISCV_PCREL_HI20: /* S + A - P */
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{
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val = (int32)(intptr_t)((uint8 *)symbol_addr - addr);
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val = (int32)(intptr_t)((uint8 *)symbol_addr + reloc_addend - addr);
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CHECK_RELOC_OFFSET(sizeof(uint32));
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if (val != (intptr_t)((uint8 *)symbol_addr - addr)) {
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if (val != (intptr_t)((uint8 *)symbol_addr + reloc_addend - addr)) {
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if (symbol_index >= 0) {
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/* Call runtime function by plt code */
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symbol_addr = (uint8 *)module->code + module->code_size
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@ -351,7 +369,7 @@ apply_relocation(AOTModule *module, uint8 *target_section_addr,
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}
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}
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if (val != (intptr_t)((uint8 *)symbol_addr - addr)) {
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if (val != (intptr_t)((uint8 *)symbol_addr + reloc_addend - addr)) {
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goto fail_addr_out_of_range;
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}
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@ -372,32 +390,15 @@ apply_relocation(AOTModule *module, uint8 *target_section_addr,
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break;
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}
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case R_RISCV_HI20: /* S + A */
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case R_RISCV_PCREL_HI20: /* S + A - P */
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case R_RISCV_HI20: /* S + A */
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{
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if (reloc_type == R_RISCV_PCREL_HI20) {
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val = (int32)((intptr_t)symbol_addr + (intptr_t)reloc_addend
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- (intptr_t)addr);
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}
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else {
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val = (int32)((intptr_t)symbol_addr + (intptr_t)reloc_addend);
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}
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val = (int32)((intptr_t)symbol_addr + (intptr_t)reloc_addend);
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CHECK_RELOC_OFFSET(sizeof(uint32));
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if (reloc_type == R_RISCV_PCREL_HI20) {
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if (val
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!= ((intptr_t)symbol_addr + (intptr_t)reloc_addend
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- (intptr_t)addr)) {
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goto fail_addr_out_of_range;
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}
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}
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else {
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if (val != ((intptr_t)symbol_addr + (intptr_t)reloc_addend)) {
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goto fail_addr_out_of_range;
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}
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if (val != ((intptr_t)symbol_addr + (intptr_t)reloc_addend)) {
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goto fail_addr_out_of_range;
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}
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addr = target_section_addr + reloc_offset;
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insn = rv_get_val((uint16 *)addr);
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rv_calc_imm(val, &imm_hi, &imm_lo);
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insn = (insn & 0x00000fff) | (imm_hi << 12);
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@ -405,27 +406,44 @@ apply_relocation(AOTModule *module, uint8 *target_section_addr,
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break;
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}
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case R_RISCV_LO12_I: /* S + A */
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case R_RISCV_PCREL_LO12_I: /* S - P */
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case R_RISCV_PCREL_LO12_S: /* S - P */
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{
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if (reloc_type == R_RISCV_PCREL_LO12_I) {
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/* A = 0 */
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val = (int32)((intptr_t)symbol_addr - (intptr_t)addr);
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}
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else {
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val = (int32)((intptr_t)symbol_addr + (intptr_t)reloc_addend);
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/* Already handled in R_RISCV_PCREL_HI20, it should be skipped for
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* most cases. But it is still needed for some special cases, e.g.
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* ```
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* label:
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* auipc t0, %pcrel_hi(symbol) # R_RISCV_PCREL_HI20 (symbol)
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* lui t1, 1
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* lw t2, t0, %pcrel_lo(label) # R_RISCV_PCREL_LO12_I (label)
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* add t2, t2, t1
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* sw t2, t0, %pcrel_lo(label) # R_RISCV_PCREL_LO12_S (label)
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* ```
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* In this case, the R_RISCV_PCREL_LO12_I/S relocation should be
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* handled after R_RISCV_PCREL_HI20 relocation.
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*
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* So, if the R_RISCV_PCREL_LO12_I/S relocation is not followed by
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* R_RISCV_PCREL_HI20 relocation, it should be handled here but
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* not implemented yet.
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*/
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if ((uintptr_t)addr - (uintptr_t)symbol_addr
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- (uintptr_t)reloc_addend
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!= 4) {
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goto fail_addr_out_of_range;
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}
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break;
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}
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case R_RISCV_LO12_I: /* S + A */
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{
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val = (int32)((intptr_t)symbol_addr + (intptr_t)reloc_addend);
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CHECK_RELOC_OFFSET(sizeof(uint32));
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if (reloc_type == R_RISCV_PCREL_LO12_I) {
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if (val != (intptr_t)symbol_addr - (intptr_t)addr) {
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goto fail_addr_out_of_range;
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}
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}
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else {
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if (val != (intptr_t)symbol_addr + (intptr_t)reloc_addend) {
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goto fail_addr_out_of_range;
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}
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if (val != (intptr_t)symbol_addr + (intptr_t)reloc_addend) {
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goto fail_addr_out_of_range;
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}
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addr = target_section_addr + reloc_offset;
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@ -1072,6 +1072,17 @@ def compile_wasm_to_aot(wasm_tempfile, aot_tempfile, runner, opts, r, output = '
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# exception isn't thrown in several cases
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cmd.append("--disable-llvm-lto")
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# Bounds checks is disabled by default for 64-bit targets, to
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# use the hardware based bounds checks. But it is not supported
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# in QEMU with NuttX.
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# Enable bounds checks explicitly for all targets if running in QEMU.
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if opts.qemu:
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cmd.append("--bounds-checks=1")
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# RISCV64 requires -mcmodel=medany, which can be set by --size-level=1
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if test_target.startswith("riscv64"):
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cmd.append("--size-level=1")
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cmd += ["-o", aot_tempfile, wasm_tempfile]
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log("Running: %s" % " ".join(cmd))
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