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Re-organize intrinsics in aot_reloc_riscv.c to fix some FPU issues (#2414)

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Huang Qi 2023-08-01 17:28:57 +08:00 committed by GitHub
parent 8518197053
commit 4b1f027690
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 15 additions and 19 deletions
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34
core/iwasm/aot/arch/aot_reloc_riscv.c
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@ -78,6 +78,13 @@ static SymbolMap target_sym_map[] = {
REG_SYM(__addsf3),
REG_SYM(__divdf3),
REG_SYM(__divsf3),
REG_SYM(__eqdf2),
REG_SYM(__eqsf2),
REG_SYM(__extendsfdf2),
REG_SYM(__fixunsdfdi),
REG_SYM(__fixunsdfsi),
REG_SYM(__fixunssfdi),
REG_SYM(__fixunssfsi),
REG_SYM(__gedf2),
REG_SYM(__gesf2),
REG_SYM(__gtdf2),
@ -89,44 +96,33 @@ static SymbolMap target_sym_map[] = {
REG_SYM(__muldf3),
REG_SYM(__nedf2),
REG_SYM(__nesf2),
REG_SYM(__eqsf2),
REG_SYM(__eqdf2),
REG_SYM(__extendsfdf2),
REG_SYM(__fixunsdfdi),
REG_SYM(__fixunsdfsi),
REG_SYM(__fixunssfsi),
REG_SYM(__subdf3),
REG_SYM(__subsf3),
REG_SYM(__truncdfsf2),
REG_SYM(__unorddf2),
REG_SYM(__unordsf2),
#endif
REG_SYM(__divdi3),
REG_SYM(__divsi3),
#if __riscv_xlen == 32
REG_SYM(__fixdfdi),
REG_SYM(__fixdfsi),
REG_SYM(__fixsfdi),
REG_SYM(__fixsfsi),
#endif
REG_SYM(__fixunssfdi),
#if __riscv_xlen == 32
REG_SYM(__floatdidf),
REG_SYM(__floatdisf),
REG_SYM(__floatsisf),
REG_SYM(__floatsidf),
REG_SYM(__floatsisf),
REG_SYM(__floatundidf),
REG_SYM(__floatundisf),
REG_SYM(__floatunsisf),
REG_SYM(__floatunsidf),
#endif
REG_SYM(__moddi3),
REG_SYM(__modsi3),
REG_SYM(__muldi3),
#if __riscv_xlen == 32
REG_SYM(__floatunsisf),
REG_SYM(__mulsf3),
REG_SYM(__mulsi3),
#endif
#endif
REG_SYM(__divdi3),
REG_SYM(__divsi3),
REG_SYM(__moddi3),
REG_SYM(__modsi3),
REG_SYM(__muldi3),
REG_SYM(__udivdi3),
REG_SYM(__udivsi3),
REG_SYM(__umoddi3),