diff --git a/.github/workflows/spec_test_on_nuttx.yml b/.github/workflows/spec_test_on_nuttx.yml index 1ae3bdf04..059e5fbef 100644 --- a/.github/workflows/spec_test_on_nuttx.yml +++ b/.github/workflows/spec_test_on_nuttx.yml @@ -74,6 +74,11 @@ jobs: target: "riscv32", fpu_type: "none" }, + { + config: "boards/risc-v/qemu-rv/rv-virt/configs/nsh", + target: "riscv32_ilp32f", + fpu_type: "fp" + }, # { # config: "boards/risc-v/qemu-rv/rv-virt/configs/nsh", # target: "riscv32_ilp32d", @@ -120,6 +125,10 @@ jobs: - target_config: { config: "boards/risc-v/qemu-rv/rv-virt/configs/nsh64" } wamr_test_option: { mode: "-t aot -X" } + # XIP is not fully supported yet on RISCV32 ILP32F, some relocations can not be resolved + - target_config: { config: "boards/risc-v/qemu-rv/rv-virt/configs/nsh", fpu_type: "fp" } + wamr_test_option: { mode: "-t aot -X" } + # Our xtensa environment doesn't have enough memory - target_config: { target: "xtensa" } wamr_feature_option: { mode: "-G" } diff --git a/build-scripts/config_common.cmake b/build-scripts/config_common.cmake index 10d1289eb..d4dd2c0d6 100644 --- a/build-scripts/config_common.cmake +++ b/build-scripts/config_common.cmake @@ -39,6 +39,8 @@ elseif (WAMR_BUILD_TARGET STREQUAL "RISCV64_LP64") add_definitions(-DBUILD_TARGET_RISCV64_LP64) elseif (WAMR_BUILD_TARGET STREQUAL "RISCV32" OR WAMR_BUILD_TARGET STREQUAL "RISCV32_ILP32D") add_definitions(-DBUILD_TARGET_RISCV32_ILP32D) +elseif (WAMR_BUILD_TARGET STREQUAL "RISCV32_ILP32F") + add_definitions(-DBUILD_TARGET_RISCV32_ILP32F) elseif (WAMR_BUILD_TARGET STREQUAL "RISCV32_ILP32") add_definitions(-DBUILD_TARGET_RISCV32_ILP32) elseif (WAMR_BUILD_TARGET STREQUAL "ARC") diff --git a/core/config.h b/core/config.h index 9fd540f32..7c783dd32 100644 --- a/core/config.h +++ b/core/config.h @@ -20,6 +20,7 @@ && !defined(BUILD_TARGET_RISCV64_LP64D) \ && !defined(BUILD_TARGET_RISCV64_LP64) \ && !defined(BUILD_TARGET_RISCV32_ILP32D) \ + && !defined(BUILD_TARGET_RISCV32_ILP32F) \ && !defined(BUILD_TARGET_RISCV32_ILP32) \ && !defined(BUILD_TARGET_ARC) /* clang-format on */ @@ -43,7 +44,11 @@ #define BUILD_TARGET_XTENSA #elif defined(__riscv) && (__riscv_xlen == 64) #define BUILD_TARGET_RISCV64_LP64D -#elif defined(__riscv) && (__riscv_xlen == 32) +#elif defined(__riscv) && (__riscv_xlen == 32) && !defined(__riscv_flen) +#define BUILD_TARGET_RISCV32_ILP32 +#elif defined(__riscv) && (__riscv_xlen == 32) && (__riscv_flen == 32) +#define BUILD_TARGET_RISCV32_ILP32F +#elif defined(__riscv) && (__riscv_xlen == 32) && (__riscv_flen == 64) #define BUILD_TARGET_RISCV32_ILP32D #elif defined(__arc__) #define BUILD_TARGET_ARC diff --git a/core/iwasm/common/wasm_runtime_common.c b/core/iwasm/common/wasm_runtime_common.c index 8ed14ec40..37a89f8fb 100644 --- a/core/iwasm/common/wasm_runtime_common.c +++ b/core/iwasm/common/wasm_runtime_common.c @@ -4718,9 +4718,13 @@ fail: * Implementation of wasm_runtime_invoke_native() */ -/* The invoke native implementation on ARM platform with VFP co-processor */ +/** + * The invoke native implementation on ARM platform with VFP co-processor, + * RISCV32 platform with/without FPU/DPFPU and ARC platform. + */ #if defined(BUILD_TARGET_ARM_VFP) || defined(BUILD_TARGET_THUMB_VFP) \ || defined(BUILD_TARGET_RISCV32_ILP32D) \ + || defined(BUILD_TARGET_RISCV32_ILP32F) \ || defined(BUILD_TARGET_RISCV32_ILP32) || defined(BUILD_TARGET_ARC) typedef void (*GenericFunctionPointer)(); void @@ -4821,7 +4825,8 @@ wasm_runtime_invoke_native(WASMExecEnv *exec_env, void *func_ptr, #endif n_ints += 2; } -#if defined(BUILD_TARGET_RISCV32_ILP32) \ +#if defined(BUILD_TARGET_RISCV32_ILP32) \ + || defined(BUILD_TARGET_RISCV32_ILP32F) \ || defined(BUILD_TARGET_RISCV32_ILP32D) || defined(BUILD_TARGET_ARC) /* part in register, part in stack */ else if (n_ints == MAX_REG_INTS - 1) { @@ -4843,19 +4848,32 @@ wasm_runtime_invoke_native(WASMExecEnv *exec_env, void *func_ptr, case VALUE_TYPE_F32: if (n_fps < MAX_REG_FLOATS) n_fps++; +#if defined(BUILD_TARGET_RISCV32_ILP32F) + else if (n_ints < MAX_REG_INTS) { + n_ints++; + } +#endif else n_stacks++; break; case VALUE_TYPE_F64: +#if defined(BUILD_TARGET_RISCV32_ILP32) \ + || defined(BUILD_TARGET_RISCV32_ILP32F) || defined(BUILD_TARGET_ARC) + if (n_ints < MAX_REG_INTS - 1) { + n_ints += 2; + } + else if (n_ints == MAX_REG_INTS - 1) { + n_ints++; + n_stacks++; + } +#endif +#if defined(BUILD_TARGET_ARM_VFP) || defined(BUILD_TARGET_THUMB_VFP) if (n_fps < MAX_REG_FLOATS - 1) { -#if !defined(BUILD_TARGET_RISCV32_ILP32) && !defined(BUILD_TARGET_ARC) /* 64-bit data must be 8 bytes aligned in arm */ if (n_fps & 1) n_fps++; -#endif n_fps += 2; } -#if defined(BUILD_TARGET_RISCV32_ILP32) || defined(BUILD_TARGET_ARC) else if (n_fps == MAX_REG_FLOATS - 1) { n_fps++; n_stacks++; @@ -4887,7 +4905,7 @@ wasm_runtime_invoke_native(WASMExecEnv *exec_env, void *func_ptr, /* use int regs firstly if available */ if (n_ints & 1) n_ints++; - ints += 2; + n_ints += 2; } else { /* 64-bit data in stack must be 8 bytes aligned in riscv32 @@ -4911,7 +4929,8 @@ wasm_runtime_invoke_native(WASMExecEnv *exec_env, void *func_ptr, n_stacks++; } -#if defined(BUILD_TARGET_ARM_VFP) || defined(BUILD_TARGET_THUMB_VFP) +#if defined(BUILD_TARGET_ARM_VFP) || defined(BUILD_TARGET_THUMB_VFP) \ + || defined(BUILD_TARGET_RISCV32_ILP32F) argc1 = MAX_REG_INTS + MAX_REG_FLOATS + n_stacks; #elif defined(BUILD_TARGET_RISCV32_ILP32) || defined(BUILD_TARGET_ARC) argc1 = MAX_REG_INTS + n_stacks; @@ -4928,7 +4947,8 @@ wasm_runtime_invoke_native(WASMExecEnv *exec_env, void *func_ptr, } ints = argv1; -#if defined(BUILD_TARGET_ARM_VFP) || defined(BUILD_TARGET_THUMB_VFP) +#if defined(BUILD_TARGET_ARM_VFP) || defined(BUILD_TARGET_THUMB_VFP) \ + || defined(BUILD_TARGET_RISCV32_ILP32F) fps = ints + MAX_REG_INTS; stacks = fps + MAX_REG_FLOATS; #elif defined(BUILD_TARGET_RISCV32_ILP32) || defined(BUILD_TARGET_ARC) @@ -5018,7 +5038,8 @@ wasm_runtime_invoke_native(WASMExecEnv *exec_env, void *func_ptr, ints[n_ints++] = *argv_src++; ints[n_ints++] = *argv_src++; } -#if defined(BUILD_TARGET_RISCV32_ILP32) \ +#if defined(BUILD_TARGET_RISCV32_ILP32) \ + || defined(BUILD_TARGET_RISCV32_ILP32F) \ || defined(BUILD_TARGET_RISCV32_ILP32D) || defined(BUILD_TARGET_ARC) else if (n_ints == MAX_REG_INTS - 1) { ints[n_ints++] = *argv_src++; @@ -5042,22 +5063,36 @@ wasm_runtime_invoke_native(WASMExecEnv *exec_env, void *func_ptr, { if (n_fps < MAX_REG_FLOATS) *(float32 *)&fps[n_fps++] = *(float32 *)argv_src++; +#if defined(BUILD_TARGET_RISCV32_ILP32F) + else if (n_ints < MAX_REG_INTS) { + ints[n_ints++] = *argv_src++; + } +#endif else *(float32 *)&stacks[n_stacks++] = *(float32 *)argv_src++; break; } case VALUE_TYPE_F64: { +#if defined(BUILD_TARGET_RISCV32_ILP32) \ + || defined(BUILD_TARGET_RISCV32_ILP32F) || defined(BUILD_TARGET_ARC) + if (n_ints < MAX_REG_INTS - 1) { + ints[n_ints++] = *argv_src++; + ints[n_ints++] = *argv_src++; + } + else if (n_ints == MAX_REG_INTS - 1) { + ints[n_ints++] = *argv_src++; + stacks[n_stacks++] = *argv_src++; + } +#endif +#if defined(BUILD_TARGET_ARM_VFP) || defined(BUILD_TARGET_THUMB_VFP) if (n_fps < MAX_REG_FLOATS - 1) { -#if !defined(BUILD_TARGET_RISCV32_ILP32) && !defined(BUILD_TARGET_ARC) /* 64-bit data must be 8 bytes aligned in arm */ if (n_fps & 1) n_fps++; -#endif fps[n_fps++] = *argv_src++; fps[n_fps++] = *argv_src++; } -#if defined(BUILD_TARGET_RISCV32_ILP32) || defined(BUILD_TARGET_ARC) else if (n_fps == MAX_REG_FLOATS - 1) { fps[n_fps++] = *argv_src++; stacks[n_stacks++] = *argv_src++; @@ -5249,6 +5284,7 @@ fail: #endif /* end of defined(BUILD_TARGET_ARM_VFP) \ || defined(BUILD_TARGET_THUMB_VFP) \ || defined(BUILD_TARGET_RISCV32_ILP32D) \ + || defined(BUILD_TARGET_RISCV32_ILP32F) \ || defined(BUILD_TARGET_RISCV32_ILP32) \ || defined(BUILD_TARGET_ARC) */ diff --git a/doc/build_wamr.md b/doc/build_wamr.md index 181f32ca0..2adb17f6a 100644 --- a/doc/build_wamr.md +++ b/doc/build_wamr.md @@ -28,7 +28,7 @@ The script `runtime_lib.cmake` defines a number of variables for configuring the - For ARM and THUMB, the format is \\[\]\[_VFP], where \ is the ARM sub-architecture and the "_VFP" suffix means using VFP coprocessor registers s0-s15 (d0-d7) for passing arguments or returning results in standard procedure-call. Both \ and "_VFP" are optional, e.g. ARMV7, ARMV7_VFP, THUMBV7, THUMBV7_VFP and so on. - For AARCH64, the format is\[\], VFP is enabled by default. \ is optional, e.g. AARCH64, AARCH64V8, AARCH64V8.1 and so on. - For RISCV64, the format is \[_abi], where "_abi" is optional, currently the supported formats are RISCV64, RISCV64_LP64D and RISCV64_LP64: RISCV64 and RISCV64_LP64D are identical, using [LP64D](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc#named-abis) as abi (LP64 with hardware floating-point calling convention for FLEN=64). And RISCV64_LP64 uses [LP64](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc#named-abis) as abi (Integer calling-convention only, and hardware floating-point calling convention is not used). - - For RISCV32, the format is \[_abi], where "_abi" is optional, currently the supported formats are RISCV32, RISCV32_ILP32D and RISCV32_ILP32: RISCV32 and RISCV32_ILP32D are identical, using [ILP32D](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc#named-abis) as abi (ILP32 with hardware floating-point calling convention for FLEN=64). And RISCV32_ILP32 uses [ILP32](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc#named-abis) as abi (Integer calling-convention only, and hardware floating-point calling convention is not used). + - For RISCV32, the format is \[_abi], where "_abi" is optional, currently the supported formats are RISCV32, RISCV32_ILP32D, RISCV32_ILP32F and RISCV32_ILP32: RISCV32 and RISCV32_ILP32D are identical, using [ILP32D](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc#named-abis) as abi (ILP32 with hardware floating-point calling convention for FLEN=64). RISCV32_ILP32F uses [ILP32F](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc#named-abis) as abi (ILP32 with hardware floating-point calling convention for FLEN=32). And RISCV32_ILP32 uses [ILP32](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc#named-abis) as abi (Integer calling-convention only, and hardware floating-point calling convention is not used). ```bash cmake -DWAMR_BUILD_PLATFORM=linux -DWAMR_BUILD_TARGET=ARM diff --git a/product-mini/platforms/nuttx/wamr.mk b/product-mini/platforms/nuttx/wamr.mk index 6e1f9ff7e..38553e863 100644 --- a/product-mini/platforms/nuttx/wamr.mk +++ b/product-mini/platforms/nuttx/wamr.mk @@ -101,10 +101,10 @@ else ifeq (${WAMR_BUILD_TARGET}, RISCV32) ifeq (${CONFIG_ARCH_DPFPU},y) CFLAGS += -DBUILD_TARGET_RISCV32_ILP32D -else ifneq (${CONFIG_ARCH_FPU},y) - CFLAGS += -DBUILD_TARGET_RISCV32_ILP32 +else ifeq (${CONFIG_ARCH_FPU},y) + CFLAGS += -DBUILD_TARGET_RISCV32_ILP32F else - $(error riscv32 ilp32f is unsupported) + CFLAGS += -DBUILD_TARGET_RISCV32_ILP32 endif INVOKE_NATIVE += invokeNative_riscv.S diff --git a/wamr-compiler/CMakeLists.txt b/wamr-compiler/CMakeLists.txt index 245b4a031..2ab0462b2 100644 --- a/wamr-compiler/CMakeLists.txt +++ b/wamr-compiler/CMakeLists.txt @@ -121,6 +121,8 @@ elseif (WAMR_BUILD_TARGET STREQUAL "RISCV64_LP64") add_definitions(-DBUILD_TARGET_RISCV64_LP64) elseif (WAMR_BUILD_TARGET STREQUAL "RISCV32" OR WAMR_BUILD_TARGET STREQUAL "RISCV32_ILP32D") add_definitions(-DBUILD_TARGET_RISCV32_ILP32D) +elseif (WAMR_BUILD_TARGET STREQUAL "RISCV32_ILP32F") + add_definitions(-DBUILD_TARGET_RISCV32_ILP32F) elseif (WAMR_BUILD_TARGET STREQUAL "RISCV32_ILP32") add_definitions(-DBUILD_TARGET_RISCV32_ILP32) else ()