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CI: Enable XIP spectest for RISCV32 ILP32F (#3727)

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Huang Qi 2024-08-19 09:52:38 +08:00 committed by GitHub
parent 4c127715df
commit 67c33a29e3
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2 changed files with 2 additions and 5 deletions
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4
.github/workflows/spec_test_on_nuttx.yml vendored
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@ -125,10 +125,6 @@ jobs:
- target_config: { config: "boards/risc-v/qemu-rv/rv-virt/configs/nsh64" } - target_config: { config: "boards/risc-v/qemu-rv/rv-virt/configs/nsh64" }
wamr_test_option: { mode: "-t aot -X" } wamr_test_option: { mode: "-t aot -X" }
# XIP is not fully supported yet on RISCV32 ILP32F, some relocations can not be resolved
- target_config: { config: "boards/risc-v/qemu-rv/rv-virt/configs/nsh", fpu_type: "fp" }
wamr_test_option: { mode: "-t aot -X" }
# Our xtensa environment doesn't have enough memory # Our xtensa environment doesn't have enough memory
- target_config: { target: "xtensa" } - target_config: { target: "xtensa" }
wamr_feature_option: { mode: "-G" } wamr_feature_option: { mode: "-G" }

3
tests/wamr-test-suites/spec-test-script/runtest.py
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@ -65,7 +65,8 @@ aot_target_options_map = {
# AOT compilation options mapping for XIP mode # AOT compilation options mapping for XIP mode
aot_target_options_map_xip = { aot_target_options_map_xip = {
# avoid l32r relocations for xtensa # avoid l32r relocations for xtensa
"xtensa": ["--mllvm=-mtext-section-literals"] "xtensa": ["--mllvm=-mtext-section-literals"],
"riscv32_ilp32f": ["--enable-builtin-intrinsics=i64.common,f64.common,f32.const,f64.const,f64xi32,f64xi64,f64_promote_f32,f32_demote_f64"],
} }
def debug(data): def debug(data):