mirror of
https://github.com/bytecodealliance/wasm-micro-runtime.git
synced 2025-06-18 02:59:21 +00:00
Fix fast jit issues (#1208)
Move jit spill cache to the end of interp frame to reduce footprint Fix codegen compare float issue: should not overwritten the source registers Fix float to int conversion check integer overflow issue Unify the float compare Fix get_global issue
This commit is contained in:
Wenyong Huang
GitHub
parent
5e9f08fb68
commit
ab2e959616
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@ -102,12 +102,6 @@
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#define WASM_ENABLE_FAST_JIT_DUMP 0
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#endif
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#ifndef FAST_JIT_SPILL_CACHE_SIZE
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/* The size of fast jit spill cache in cell num, one cell num
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occpuies 4 bytes */
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#define FAST_JIT_SPILL_CACHE_SIZE 32
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#endif
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#ifndef WASM_ENABLE_WAMR_COMPILER
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#define WASM_ENABLE_WAMR_COMPILER 0
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#endif
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@ -82,6 +82,9 @@ x86::Gp regs_i64[] = {
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x86::r12, x86::r13, x86::r14, x86::r15,
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};
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#define REG_F32_FREE_IDX 15
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#define REG_F64_FREE_IDX 15
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x86::Xmm regs_float[] = {
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x86::xmm0,
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x86::xmm1,
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@ -349,6 +352,8 @@ cmp_r_and_jmp_label(JitCompContext *cc, x86::Assembler &a,
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bool fp_cmp = cc->last_cmp_on_fp;
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bh_assert(!fp_cmp || (fp_cmp && (op == GES)));
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switch (op) {
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case EQ:
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{
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@ -362,60 +367,52 @@ cmp_r_and_jmp_label(JitCompContext *cc, x86::Assembler &a,
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}
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case GTS:
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{
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if (fp_cmp) {
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a.ja(imm);
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}
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else {
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a.jg(imm);
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}
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a.jg(imm);
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break;
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}
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case LES:
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{
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if (fp_cmp) {
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a.jnb(imm);
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}
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else {
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a.jng(imm);
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}
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a.jng(imm);
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break;
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}
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case GES:
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{
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if (fp_cmp) {
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a.jnb(imm);
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}
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else {
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if (fp_cmp)
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a.jae(imm);
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else
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a.jnl(imm);
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}
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break;
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}
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case LTS:
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{
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if (fp_cmp) {
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a.ja(imm);
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}
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else {
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a.jl(imm);
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}
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a.jl(imm);
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break;
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}
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case GTU:
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{
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a.ja(imm);
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break;
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}
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case LEU:
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{
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a.jna(imm);
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break;
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}
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case GEU:
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{
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a.jnb(imm);
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break;
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}
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case LTU:
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{
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a.jb(imm);
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break;
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}
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default:
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{
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bh_assert(0);
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break;
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}
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}
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if (r2) {
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@ -761,10 +758,17 @@ static bool
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mov_imm_to_m(x86::Assembler &a, x86::Mem &m_dst, Imm imm_src, uint32 bytes_dst)
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{
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if (bytes_dst == 8) {
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/* As there is no instruction `MOV m64, imm64`, we use
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two instructions to implement it */
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a.mov(regs_i64[REG_I64_FREE_IDX], imm_src);
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a.mov(m_dst, regs_i64[REG_I64_FREE_IDX]);
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int64 value = imm_src.value();
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if (value >= INT32_MIN && value <= INT32_MAX) {
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imm_src.setValue((int32)value);
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a.mov(m_dst, imm_src);
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}
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else {
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/* There is no instruction `MOV m64, imm64`, we use
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two instructions to implement it */
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a.mov(regs_i64[REG_I64_FREE_IDX], imm_src);
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a.mov(m_dst, regs_i64[REG_I64_FREE_IDX]);
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}
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}
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else
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a.mov(m_dst, imm_src);
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@ -4220,17 +4224,8 @@ static bool
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cmp_imm_r_to_r_f32(x86::Assembler &a, int32 reg_no_dst, float data1_src,
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int32 reg_no2_src)
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{
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const JitHardRegInfo *hreg_info = jit_codegen_get_hreg_info();
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/* xmm -> m128 */
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x86::Mem cache = x86::xmmword_ptr(regs_i64[hreg_info->exec_env_hreg_index],
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offsetof(WASMExecEnv, jit_cache));
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a.movups(cache, regs_float[reg_no2_src]);
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/* imm -> gp -> xmm */
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mov_imm_to_r_f32(a, reg_no2_src, data1_src);
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/* comiss xmm m32 */
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a.comiss(regs_float[reg_no2_src], cache);
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mov_imm_to_r_f32(a, REG_F32_FREE_IDX, data1_src);
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a.comiss(regs_float[REG_F32_FREE_IDX], regs_float[reg_no2_src]);
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return true;
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}
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@ -4249,15 +4244,8 @@ static bool
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cmp_r_imm_to_r_f32(x86::Assembler &a, int32 reg_no_dst, int32 reg_no1_src,
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float data2_src)
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{
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const JitHardRegInfo *hreg_info = jit_codegen_get_hreg_info();
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/* imm -> m32 */
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x86::Mem cache = x86::dword_ptr(regs_i64[hreg_info->exec_env_hreg_index],
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offsetof(WASMExecEnv, jit_cache));
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Imm imm(*(uint32 *)&data2_src);
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mov_imm_to_m(a, cache, imm, 4);
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/* comiss xmm m32 */
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a.comiss(regs_float[reg_no1_src], cache);
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mov_imm_to_r_f32(a, REG_F32_FREE_IDX, data2_src);
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a.comiss(regs_float[reg_no1_src], regs_float[REG_F32_FREE_IDX]);
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return true;
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}
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@ -4315,17 +4303,8 @@ static bool
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cmp_imm_r_to_r_f64(x86::Assembler &a, int32 reg_no_dst, double data1_src,
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int32 reg_no2_src)
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{
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const JitHardRegInfo *hreg_info = jit_codegen_get_hreg_info();
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/* xmm -> m128 */
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x86::Mem cache = x86::qword_ptr(regs_i64[hreg_info->exec_env_hreg_index],
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offsetof(WASMExecEnv, jit_cache));
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a.movupd(cache, regs_float[reg_no2_src]);
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/* imm -> gp -> xmm */
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mov_imm_to_r_f64(a, reg_no2_src, data1_src);
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/* comiss xmm m64 */
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a.comisd(regs_float[reg_no2_src], cache);
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mov_imm_to_r_f64(a, REG_F64_FREE_IDX, data1_src);
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a.comisd(regs_float[REG_F64_FREE_IDX], regs_float[reg_no2_src]);
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return true;
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}
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@ -4344,15 +4323,8 @@ static bool
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cmp_r_imm_to_r_f64(x86::Assembler &a, int32 reg_no_dst, int32 reg_no1_src,
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double data2_src)
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{
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const JitHardRegInfo *hreg_info = jit_codegen_get_hreg_info();
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/* imm -> m64 */
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x86::Mem cache = x86::qword_ptr(regs_i64[hreg_info->exec_env_hreg_index],
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offsetof(WASMExecEnv, jit_cache));
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Imm imm(*(uint64 *)&data2_src);
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mov_imm_to_m(a, cache, imm, 8);
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/* comisd xmm m64 */
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a.comisd(regs_float[reg_no1_src], cache);
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mov_imm_to_r_f64(a, REG_F64_FREE_IDX, data2_src);
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a.comisd(regs_float[reg_no1_src], regs_float[REG_F64_FREE_IDX]);
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return true;
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}
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@ -5071,13 +5043,19 @@ cmp_r_and_jmp_relative(JitCompContext *cc, x86::Assembler &a, int32 reg_no,
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+ a.code()->sectionById(0)->buffer().size();
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bool fp_cmp = cc->last_cmp_on_fp;
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bh_assert(!fp_cmp || (fp_cmp && (op == GTS || op == GES)));
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switch (op) {
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case EQ:
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{
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a.je(target);
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break;
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}
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case NE:
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{
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a.jne(target);
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break;
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}
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case GTS:
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{
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if (fp_cmp) {
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@ -5090,18 +5068,13 @@ cmp_r_and_jmp_relative(JitCompContext *cc, x86::Assembler &a, int32 reg_no,
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}
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case LES:
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{
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if (fp_cmp) {
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a.jnb(target);
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}
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else {
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a.jng(target);
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}
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a.jng(target);
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break;
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}
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case GES:
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{
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if (fp_cmp) {
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a.jnb(target);
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a.jae(target);
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}
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else {
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a.jnl(target);
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@ -5110,29 +5083,34 @@ cmp_r_and_jmp_relative(JitCompContext *cc, x86::Assembler &a, int32 reg_no,
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}
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case LTS:
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{
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if (fp_cmp) {
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a.ja(target);
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}
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else {
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a.jl(target);
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}
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a.jl(target);
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break;
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}
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case GTU:
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{
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a.ja(target);
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break;
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}
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case LEU:
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{
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a.jna(target);
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break;
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}
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case GEU:
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{
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a.jae(target);
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break;
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}
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case LTU:
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{
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a.jb(target);
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break;
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}
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default:
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{
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bh_assert(0);
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break;
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}
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}
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/* The offset written by asmjit is always 0, we patch it again */
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@ -5174,10 +5152,13 @@ lower_select(JitCompContext *cc, x86::Assembler &a, COND_OP op, JitReg r0,
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CHECK_NCONST(r1);
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CHECK_KIND(r1, JIT_REG_KIND_I32);
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if (r0 == r3 && r0 != r2) {
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if (r0 == r3 && r0 != r2 && !cc->last_cmp_on_fp) {
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JitReg r_tmp;
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/* Exchange r2, r3*/
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/* For i32/i64, exchange r2 and r3 to make r0 equal to r2,
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so as to decrease possible execution instructions.
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For f32/f64 comparison, should not change the order as
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the result of comparison with NaN may be different. */
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r_tmp = r2;
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r2 = r3;
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r3 = r_tmp;
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@ -5258,7 +5239,8 @@ lower_branch(JitCompContext *cc, x86::Assembler &a, bh_list *jmp_info_list,
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label_dst = jit_reg_no(r1);
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if (label_dst < (int32)jit_cc_label_num(cc) - 1 && is_last_insn
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&& label_is_neighboring(cc, label_src, label_dst)) {
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&& label_is_neighboring(cc, label_src, label_dst)
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&& !cc->last_cmp_on_fp) {
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JitReg r_tmp;
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r_tmp = r1;
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@ -6555,20 +6537,20 @@ static uint8 hreg_info_F32[3][16] = {
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{ 0, 0, 0, 0, 0, 0, 0, 0,
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1, 1, 1, 1, 1, 1, 1, 1 },
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{ 1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1 }, /* caller_saved_native */
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1, 1, 1, 1, 1, 1, 1, 0 }, /* caller_saved_native */
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{ 1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1 }, /* caller_saved_jitted */
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1, 1, 1, 1, 1, 1, 1, 0 }, /* caller_saved_jitted */
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};
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/* System V AMD64 ABI Calling Conversion. [XYZ]MM0-7 */
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static uint8 hreg_info_F64[3][16] = {
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/* xmm0 ~ xmm15 */
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{ 1, 1, 1, 1, 1, 1, 1, 1,
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0, 0, 0, 0, 0, 0, 0, 0 },
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0, 0, 0, 0, 0, 0, 0, 1 },
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{ 1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1 }, /* caller_saved_native */
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1, 1, 1, 1, 1, 1, 1, 0 }, /* caller_saved_native */
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{ 1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1 }, /* caller_saved_jitted */
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1, 1, 1, 1, 1, 1, 1, 0 }, /* caller_saved_jitted */
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};
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static const JitHardRegInfo hreg_info = {
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@ -187,7 +187,7 @@ jit_compile_op_compare_float_point(JitCompContext *cc, FloatCond cond,
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case FLOAT_LT:
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{
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GEN_INSN(CMP, cc->cmp_reg, rhs, lhs);
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GEN_INSN(SELECTLTS, res, cc->cmp_reg, const_one, const_zero);
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GEN_INSN(SELECTGTS, res, cc->cmp_reg, const_one, const_zero);
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break;
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}
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case FLOAT_GT:
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@ -199,7 +199,7 @@ jit_compile_op_compare_float_point(JitCompContext *cc, FloatCond cond,
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case FLOAT_LE:
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{
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GEN_INSN(CMP, cc->cmp_reg, rhs, lhs);
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GEN_INSN(SELECTLES, res, cc->cmp_reg, const_one, const_zero);
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GEN_INSN(SELECTGES, res, cc->cmp_reg, const_one, const_zero);
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break;
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}
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case FLOAT_GE:
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|
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@ -63,8 +63,8 @@ jit_compile_op_i32_trunc_f32(JitCompContext *cc, bool sign, bool saturating)
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}
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/* If value is out of integer range, throw exception */
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GEN_INSN(CMP, cc->cmp_reg, value, min_valid_float);
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if (!jit_emit_exception(cc, EXCE_INTEGER_OVERFLOW, JIT_OP_BLES,
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GEN_INSN(CMP, cc->cmp_reg, min_valid_float, value);
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if (!jit_emit_exception(cc, EXCE_INTEGER_OVERFLOW, JIT_OP_BGES,
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cc->cmp_reg, NULL)) {
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goto fail;
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}
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@ -123,8 +123,8 @@ jit_compile_op_i32_trunc_f64(JitCompContext *cc, bool sign, bool saturating)
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}
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/* If value is out of integer range, throw exception */
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GEN_INSN(CMP, cc->cmp_reg, value, min_valid_double);
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if (!jit_emit_exception(cc, EXCE_INTEGER_OVERFLOW, JIT_OP_BLES,
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GEN_INSN(CMP, cc->cmp_reg, min_valid_double, value);
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if (!jit_emit_exception(cc, EXCE_INTEGER_OVERFLOW, JIT_OP_BGES,
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cc->cmp_reg, NULL)) {
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goto fail;
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}
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@ -165,7 +165,16 @@ fail:
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static uint8
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get_global_type(const WASMModule *module, uint32 global_idx)
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{
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return module->globals[global_idx].type;
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if (global_idx < module->import_global_count) {
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const WASMGlobalImport *import_global =
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&((module->import_globals + global_idx)->u.global);
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return import_global->type;
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}
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else {
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const WASMGlobal *global =
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module->globals + (global_idx - module->import_global_count);
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return global->type;
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}
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}
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static uint32
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@ -177,7 +186,8 @@ get_global_data_offset(const WASMModule *module, uint32 global_idx)
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return import_global->data_offset;
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}
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else {
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const WASMGlobal *global = module->globals + global_idx;
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const WASMGlobal *global =
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module->globals + (global_idx - module->import_global_count);
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return global->data_offset;
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}
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}
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|
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@ -332,6 +332,12 @@ jit_pass_dump(JitCompContext *cc)
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const char *pass_name =
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pass_no > 0 ? jit_compiler_get_pass_name(passes[pass_no - 1]) : "NULL";
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#if defined(BUILD_TARGET_X86_64) || defined(BUILD_TARGET_AMD_64)
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if (!strcmp(pass_name, "lower_cg"))
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/* Ignore lower codegen pass as it does nothing in x86-64 */
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return true;
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#endif
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os_printf("JIT.COMPILER.DUMP: PASS_NO=%d PREV_PASS=%s\n\n", pass_no,
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pass_name);
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jit_dump_cc(cc);
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|||
|
|
@ -755,9 +755,11 @@ init_func_translation(JitCompContext *cc)
|
|||
|
||||
cc->jit_frame = jit_frame;
|
||||
cc->cur_basic_block = jit_cc_entry_basic_block(cc);
|
||||
cc->total_frame_size = wasm_interp_interp_frame_size(total_cell_num);
|
||||
cc->spill_cache_offset = (uint32)offsetof(WASMInterpFrame, spill_cache);
|
||||
cc->spill_cache_size = (uint32)sizeof(uint32) * FAST_JIT_SPILL_CACHE_SIZE;
|
||||
cc->spill_cache_offset = wasm_interp_interp_frame_size(total_cell_num);
|
||||
/* Set spill cache size according to max local cell num, max stack cell
|
||||
num and virtual fixed register num */
|
||||
cc->spill_cache_size = (max_locals + max_stacks) * 4 + sizeof(void *) * 4;
|
||||
cc->total_frame_size = cc->spill_cache_offset + cc->spill_cache_size;
|
||||
cc->jitted_return_address_offset =
|
||||
offsetof(WASMInterpFrame, jitted_return_addr);
|
||||
cc->cur_basic_block = jit_cc_entry_basic_block(cc);
|
||||
|
|
@ -838,7 +840,7 @@ free_block_memory(JitBlock *block)
|
|||
jit_free(block);
|
||||
}
|
||||
|
||||
static JitBlock *
|
||||
static JitBasicBlock *
|
||||
create_func_block(JitCompContext *cc)
|
||||
{
|
||||
JitBlock *jit_block;
|
||||
|
|
@ -883,7 +885,7 @@ create_func_block(JitCompContext *cc)
|
|||
jit_block_stack_push(&cc->block_stack, jit_block);
|
||||
cc->cur_basic_block = jit_block->basic_block_entry;
|
||||
|
||||
return jit_block;
|
||||
return jit_block->basic_block_entry;
|
||||
|
||||
fail:
|
||||
free_block_memory(jit_block);
|
||||
|
|
@ -2086,13 +2088,13 @@ JitBasicBlock *
|
|||
jit_frontend_translate_func(JitCompContext *cc)
|
||||
{
|
||||
JitFrame *jit_frame;
|
||||
JitBlock *jit_block;
|
||||
JitBasicBlock *basic_block_entry;
|
||||
|
||||
if (!(jit_frame = init_func_translation(cc))) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (!(jit_block = create_func_block(cc))) {
|
||||
if (!(basic_block_entry = create_func_block(cc))) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
|
@ -2100,7 +2102,7 @@ jit_frontend_translate_func(JitCompContext *cc)
|
|||
return NULL;
|
||||
}
|
||||
|
||||
return jit_block->basic_block_entry;
|
||||
return basic_block_entry;
|
||||
}
|
||||
|
||||
#if 0
|
||||
|
|
|
|||
|
|
@ -28,7 +28,6 @@ typedef struct WASMInterpFrame {
|
|||
|
||||
#if WASM_ENABLE_FAST_JIT != 0
|
||||
uint8 *jitted_return_addr;
|
||||
uint32 spill_cache[FAST_JIT_SPILL_CACHE_SIZE];
|
||||
#endif
|
||||
|
||||
#if WASM_ENABLE_PERF_PROFILING != 0
|
||||
|
|
@ -52,12 +51,13 @@ typedef struct WASMInterpFrame {
|
|||
WASMBranchBlock *csp_boundary;
|
||||
WASMBranchBlock *csp;
|
||||
|
||||
/* Frame data, the layout is:
|
||||
lp: param_cell_count + local_cell_count
|
||||
sp_bottom to sp_boundary: stack of data
|
||||
csp_bottom to csp_boundary: stack of block
|
||||
ref to frame end: data types of local vairables and stack data
|
||||
*/
|
||||
/**
|
||||
* Frame data, the layout is:
|
||||
* lp: parameters and local variables
|
||||
* sp_bottom to sp_boundary: wasm operand stack
|
||||
* csp_bottom to csp_boundary: wasm label stack
|
||||
* jit spill cache: only available for fast jit
|
||||
*/
|
||||
uint32 lp[1];
|
||||
#endif
|
||||
} WASMInterpFrame;
|
||||
|
|
|
|||
|
|
@ -1509,8 +1509,8 @@ wasm_instantiate(WASMModule *module, bool is_sub_inst, uint32 stack_size,
|
|||
if (stack_size == 0)
|
||||
stack_size = DEFAULT_WASM_STACK_SIZE;
|
||||
#if WASM_ENABLE_SPEC_TEST != 0
|
||||
if (stack_size < 100 * 1024)
|
||||
stack_size = 100 * 1024;
|
||||
if (stack_size < 64 * 1024)
|
||||
stack_size = 64 * 1024;
|
||||
#endif
|
||||
module_inst->default_wasm_stack_size = stack_size;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user