From b5a67cb91edfb8604d942c4560f5add048d781e4 Mon Sep 17 00:00:00 2001 From: Wenyong Huang Date: Wed, 29 Sep 2021 11:13:38 +0800 Subject: [PATCH] Fix several issues of document, spec test script and simd (#767) Fix document issues: add ARC to supported targets, fix how to build wamrc for MacOS. Fix spec case test script issue: the latest wabt has enabled simd by default, no need to add "--enable-simd" option for test script. Fix simd LLVM IR compilation issue: using index calculated by opcode to access array element should not be out of array boundary, add bh_assert() for it. Signed-off-by: Wenyong Huang --- README.md | 2 +- core/iwasm/aot/arch/aot_reloc_riscv.c | 6 +++--- core/iwasm/common/wasm_c_api.c | 12 +++++++----- core/iwasm/compilation/simd/simd_load_store.c | 14 +++++++++++++- doc/build_wamr.md | 2 +- tests/wamr-test-suites/spec-test-script/runtest.py | 3 --- 6 files changed, 25 insertions(+), 14 deletions(-) diff --git a/README.md b/README.md index a85e99fd6..0b8103b00 100644 --- a/README.md +++ b/README.md @@ -68,7 +68,7 @@ Both wasm binary file and AoT file are supported by iwasm. The wamrc AoT compile cd wamr-compiler ./build_llvm.sh (or "./build_llvm_xtensa.sh" to support xtensa target) mkdir build && cd build -cmake .. (or "cmake .. -DWAMR_BUILD_TARGET=darwin" for MacOS) +cmake .. (or "cmake .. -DWAMR_BUILD_PLATFORM=darwin" for MacOS) make # wamrc is generated under current directory ``` diff --git a/core/iwasm/aot/arch/aot_reloc_riscv.c b/core/iwasm/aot/arch/aot_reloc_riscv.c index a5e060929..cb09b810a 100644 --- a/core/iwasm/aot/arch/aot_reloc_riscv.c +++ b/core/iwasm/aot/arch/aot_reloc_riscv.c @@ -267,7 +267,7 @@ apply_relocation(AOTModule *module, case R_RISCV_HI20: { - val = (int32)(intptr_t)(symbol_addr + reloc_addend); + val = (int32)(intptr_t)((uint8 *)symbol_addr + reloc_addend); CHECK_RELOC_OFFSET(sizeof(uint32)); if (val != (intptr_t)((uint8 *)symbol_addr + reloc_addend)) { @@ -284,7 +284,7 @@ apply_relocation(AOTModule *module, case R_RISCV_LO12_I: { - val = (int32)(intptr_t)(symbol_addr + reloc_addend); + val = (int32)(intptr_t)((uint8 *)symbol_addr + reloc_addend); CHECK_RELOC_OFFSET(sizeof(uint32)); if (val != (intptr_t)((uint8 *)symbol_addr + reloc_addend)) { @@ -301,7 +301,7 @@ apply_relocation(AOTModule *module, case R_RISCV_LO12_S: { - val = (int32)(intptr_t)(symbol_addr + reloc_addend); + val = (int32)(intptr_t)((uint8 *)symbol_addr + reloc_addend); CHECK_RELOC_OFFSET(sizeof(uint32)); if (val != (intptr_t)((uint8 *)symbol_addr + reloc_addend)) { diff --git a/core/iwasm/common/wasm_c_api.c b/core/iwasm/common/wasm_c_api.c index d79a75f4e..6bf60e2e7 100644 --- a/core/iwasm/common/wasm_c_api.c +++ b/core/iwasm/common/wasm_c_api.c @@ -2804,9 +2804,10 @@ wasm_func_call(const wasm_func_t *func, /* copy parametes */ if (param_count - && !(argc = params_to_argv(func->inst_comm_rt, params->data, - wasm_functype_params(func->type), - param_count, argv))) { + && (!params + || !(argc = params_to_argv(func->inst_comm_rt, params->data, + wasm_functype_params(func->type), + param_count, argv)))) { goto failed; } @@ -2825,8 +2826,9 @@ wasm_func_call(const wasm_func_t *func, /* copy results */ if (result_count) { - if (!(argc = argv_to_results(argv, wasm_functype_results(func->type), - result_count, results->data))) { + if (!results + || !(argc = argv_to_results(argv, wasm_functype_results(func->type), + result_count, results->data))) { goto failed; } results->num_elems = result_count; diff --git a/core/iwasm/compilation/simd/simd_load_store.c b/core/iwasm/compilation/simd/simd_load_store.c index 097974b47..3719559c9 100644 --- a/core/iwasm/compilation/simd/simd_load_store.c +++ b/core/iwasm/compilation/simd/simd_load_store.c @@ -82,7 +82,11 @@ aot_compile_simd_load_extend(AOTCompContext *comp_ctx, LLVMVectorType(INT16_TYPE, 4), LLVMVectorType(INT16_TYPE, 4), LLVMVectorType(I32_TYPE, 2), LLVMVectorType(I32_TYPE, 2), }; - LLVMTypeRef sub_vector_type = sub_vector_types[opcode_index]; + LLVMTypeRef sub_vector_type; + + bh_assert(opcode_index < 6); + + sub_vector_type = sub_vector_types[opcode_index]; /* to vector ptr type */ if (!sub_vector_type @@ -139,6 +143,8 @@ aot_compile_simd_load_splat(AOTCompContext *comp_ctx, LLVM_CONST(i32x2_zero), }; + bh_assert(opcode_index < 4); + if (!(element = simd_load(comp_ctx, func_ctx, align, offset, data_lengths[opcode_index], element_ptr_types[opcode_index]))) { @@ -179,6 +185,8 @@ aot_compile_simd_load_lane(AOTCompContext *comp_ctx, V128_i32x4_TYPE, V128_i64x2_TYPE }; LLVMValueRef lane = simd_lane_id_to_llvm_value(comp_ctx, lane_id); + bh_assert(opcode_index < 4); + if (!(vector = simd_pop_v128_and_bitcast( comp_ctx, func_ctx, vector_types[opcode_index], "src"))) { return false; @@ -225,6 +233,8 @@ aot_compile_simd_load_zero(AOTCompContext *comp_ctx, { LLVM_CONST(i32_zero), LLVM_CONST(i32_two) }, }; + bh_assert(opcode_index < 2); + if (!(element = simd_load(comp_ctx, func_ctx, align, offset, data_lengths[opcode_index], element_ptr_types[opcode_index]))) { @@ -320,6 +330,8 @@ aot_compile_simd_store_lane(AOTCompContext *comp_ctx, V128_i32x4_TYPE, V128_i64x2_TYPE }; LLVMValueRef lane = simd_lane_id_to_llvm_value(comp_ctx, lane_id); + bh_assert(opcode_index < 4); + if (!(vector = simd_pop_v128_and_bitcast( comp_ctx, func_ctx, vector_types[opcode_index], "src"))) { return false; diff --git a/doc/build_wamr.md b/doc/build_wamr.md index f11c9e640..1203008f2 100644 --- a/doc/build_wamr.md +++ b/doc/build_wamr.md @@ -19,7 +19,7 @@ The script `runtime_lib.cmake` defines a number of variables for configuring the - **WAMR_BUILD_PLATFORM**: set the target platform. It can be set to any platform name (folder name) under folder [core/shared/platform](../core/shared/platform). -- **WAMR_BUILD_TARGET**: set the target CPU architecture. Current supported targets are: X86_64, X86_32, AARCH64, ARM, THUMB, XTENSA, RISCV64 and MIPS. +- **WAMR_BUILD_TARGET**: set the target CPU architecture. Current supported targets are: X86_64, X86_32, AARCH64, ARM, THUMB, XTENSA, ARC, RISCV32, RISCV64 and MIPS. - For ARM and THUMB, the format is \\[\]\[_VFP], where \ is the ARM sub-architecture and the "_VFP" suffix means using VFP coprocessor registers s0-s15 (d0-d7) for passing arguments or returning results in standard procedure-call. Both \ and "_VFP" are optional, e.g. ARMV7, ARMV7_VFP, THUMBV7, THUMBV7_VFP and so on. - For AARCH64, the format is\[\], VFP is enabled by default. \ is optional, e.g. AARCH64, AARCH64V8, AARCH64V8.1 and so on. - For RISCV64, the format is \[_abi], where "_abi" is optional, currently the supported formats are RISCV64, RISCV64_LP64D and RISCV64_LP64: RISCV64 and RISCV64_LP64D are identical, using [LP64D](https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#-named-abis) as abi (LP64 with hardware floating-point calling convention for FLEN=64). And RISCV64_LP64 uses [LP64](https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#-named-abis) as abi (Integer calling-convention only, and hardware floating-point calling convention is not used). diff --git a/tests/wamr-test-suites/spec-test-script/runtest.py b/tests/wamr-test-suites/spec-test-script/runtest.py index 0209570c6..f79578483 100755 --- a/tests/wamr-test-suites/spec-test-script/runtest.py +++ b/tests/wamr-test-suites/spec-test-script/runtest.py @@ -902,9 +902,6 @@ def compile_wast_to_wasm(form, wast_tempfile, wasm_tempfile, opts): wast_tempfile, "-o", wasm_tempfile ] # optional arguments - if opts.simd: - cmd.append("--enable-simd") - if opts.ref_types: cmd.append("--enable-reference-types") cmd.append("--enable-bulk-memory")