gnh1201/wasm-micro-runtime
1
0
Fork 0
mirror of https://github.com/bytecodealliance/wasm-micro-runtime.git synced 2025-02-06 06:55:07 +00:00
Code Issues Actions 9 Packages Projects Releases Wiki Activity

Sync simd opcode definitions spec (#3290)

Browse Source 
Remove undefined simd opcodes.
This commit is contained in:
liang.he 2024-04-09 16:54:42 +08:00 committed by GitHub
parent 4a29794a1b
commit bcc2a2d2e1
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
11 changed files with 11 additions and 139 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

51
core/iwasm/compilation/aot_compiler.c
View File

@ -3452,16 +3452,6 @@ aot_compile_func(AOTCompContext *comp_ctx, uint32 func_index)
break;
}
case SIMD_i32x4_narrow_i64x2_s:
case SIMD_i32x4_narrow_i64x2_u:
{
if (!aot_compile_simd_i32x4_narrow_i64x2(
comp_ctx, func_ctx,
SIMD_i32x4_narrow_i64x2_s == opcode))
return false;
break;
}
case SIMD_i32x4_extend_low_i16x8_s:
case SIMD_i32x4_extend_high_i16x8_s:
{
@ -3501,16 +3491,6 @@ aot_compile_func(AOTCompContext *comp_ctx, uint32 func_index)
break;
}
case SIMD_i32x4_add_sat_s:
case SIMD_i32x4_add_sat_u:
{
if (!aot_compile_simd_i32x4_saturate(
comp_ctx, func_ctx, V128_ADD,
opcode == SIMD_i32x4_add_sat_s))
return false;
break;
}
case SIMD_i32x4_sub:
{
if (!aot_compile_simd_i32x4_arith(comp_ctx, func_ctx,
@ -3519,16 +3499,6 @@ aot_compile_func(AOTCompContext *comp_ctx, uint32 func_index)
break;
}
case SIMD_i32x4_sub_sat_s:
case SIMD_i32x4_sub_sat_u:
{
if (!aot_compile_simd_i32x4_saturate(
comp_ctx, func_ctx, V128_SUB,
opcode == SIMD_i32x4_add_sat_s))
return false;
break;
}
case SIMD_i32x4_mul:
{
if (!aot_compile_simd_i32x4_arith(comp_ctx, func_ctx,
@ -3565,13 +3535,6 @@ aot_compile_func(AOTCompContext *comp_ctx, uint32 func_index)
break;
}
case SIMD_i32x4_avgr_u:
{
if (!aot_compile_simd_i32x4_avgr_u(comp_ctx, func_ctx))
return false;
break;
}
case SIMD_i32x4_extmul_low_i16x8_s:
case SIMD_i32x4_extmul_high_i16x8_s:
{
@ -3728,13 +3691,6 @@ aot_compile_func(AOTCompContext *comp_ctx, uint32 func_index)
break;
}
case SIMD_f32x4_round:
{
if (!aot_compile_simd_f32x4_round(comp_ctx, func_ctx))
return false;
break;
}
case SIMD_f32x4_sqrt:
{
if (!aot_compile_simd_f32x4_sqrt(comp_ctx, func_ctx))
@ -3788,13 +3744,6 @@ aot_compile_func(AOTCompContext *comp_ctx, uint32 func_index)
break;
}
case SIMD_f64x2_round:
{
if (!aot_compile_simd_f64x2_round(comp_ctx, func_ctx))
return false;
break;
}
case SIMD_f64x2_sqrt:
{
if (!aot_compile_simd_f64x2_sqrt(comp_ctx, func_ctx))

9
core/iwasm/compilation/simd/simd_conversions.c
View File

@ -226,15 +226,6 @@ aot_compile_simd_i16x8_narrow_i32x4(AOTCompContext *comp_ctx,
}
}
bool
aot_compile_simd_i32x4_narrow_i64x2(AOTCompContext *comp_ctx,
AOTFuncContext *func_ctx, bool is_signed)
{
/* TODO: x86 intrinsics */
return simd_integer_narrow_common(comp_ctx, func_ctx, e_sat_i64x2,
is_signed);
}
enum integer_extend_type {
e_ext_i8x16,
e_ext_i16x8,

4
core/iwasm/compilation/simd/simd_conversions.h
View File

@ -20,10 +20,6 @@ bool
aot_compile_simd_i16x8_narrow_i32x4(AOTCompContext *comp_ctx,
AOTFuncContext *func_ctx, bool is_signed);
bool
aot_compile_simd_i32x4_narrow_i64x2(AOTCompContext *comp_ctx,
AOTFuncContext *func_ctx, bool is_signed);
bool
aot_compile_simd_i16x8_extend_i8x16(AOTCompContext *comp_ctx,
AOTFuncContext *func_ctx, bool is_low,

14
core/iwasm/compilation/simd/simd_floating_point.c
View File

@ -129,20 +129,6 @@ aot_compile_simd_f64x2_abs(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx)
"llvm.fabs.v2f64");
}
bool
aot_compile_simd_f32x4_round(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx)
{
return simd_float_intrinsic(comp_ctx, func_ctx, V128_f32x4_TYPE,
"llvm.round.v4f32");
}
bool
aot_compile_simd_f64x2_round(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx)
{
return simd_float_intrinsic(comp_ctx, func_ctx, V128_f64x2_TYPE,
"llvm.round.v2f64");
}
bool
aot_compile_simd_f32x4_sqrt(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx)
{

8
core/iwasm/compilation/simd/simd_floating_point.h
View File

@ -32,14 +32,6 @@ aot_compile_simd_f32x4_abs(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx);
bool
aot_compile_simd_f64x2_abs(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx);
bool
aot_compile_simd_f32x4_round(AOTCompContext *comp_ctx,
AOTFuncContext *func_ctx);
bool
aot_compile_simd_f64x2_round(AOTCompContext *comp_ctx,
AOTFuncContext *func_ctx);
bool
aot_compile_simd_f32x4_sqrt(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx);

11
core/iwasm/compilation/simd/simd_int_arith.c
View File

@ -243,7 +243,6 @@ aot_compile_simd_i64x2_abs(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx)
enum integer_avgr_u {
e_avgr_u_i8x16,
e_avgr_u_i16x8,
e_avgr_u_i32x4,
};
/* TODO: try int_x86_mmx_pavg_b and int_x86_mmx_pavg_w */
@ -257,9 +256,8 @@ simd_v128_avg(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx,
LLVMTypeRef vector_type[] = {
V128_i8x16_TYPE,
V128_i16x8_TYPE,
V128_i32x4_TYPE,
};
unsigned lanes[] = { 16, 8, 4 };
unsigned lanes[] = { 16, 8 };
if (!(rhs = simd_pop_v128_and_bitcast(comp_ctx, func_ctx,
vector_type[itype], "rhs"))
@ -325,13 +323,6 @@ aot_compile_simd_i16x8_avgr_u(AOTCompContext *comp_ctx,
return simd_v128_avg(comp_ctx, func_ctx, e_avgr_u_i16x8);
}
bool
aot_compile_simd_i32x4_avgr_u(AOTCompContext *comp_ctx,
AOTFuncContext *func_ctx)
{
return simd_v128_avg(comp_ctx, func_ctx, e_avgr_u_i32x4);
}
bool
aot_compile_simd_i32x4_dot_i16x8(AOTCompContext *comp_ctx,
AOTFuncContext *func_ctx)

4
core/iwasm/compilation/simd/simd_int_arith.h
View File

@ -76,10 +76,6 @@ bool
aot_compile_simd_i16x8_avgr_u(AOTCompContext *comp_ctx,
AOTFuncContext *func_ctx);
bool
aot_compile_simd_i32x4_avgr_u(AOTCompContext *comp_ctx,
AOTFuncContext *func_ctx);
bool
aot_compile_simd_i32x4_dot_i16x8(AOTCompContext *comp_ctx,
AOTFuncContext *func_ctx);

15
core/iwasm/compilation/simd/simd_sat_int_arith.c
View File

@ -64,18 +64,3 @@ aot_compile_simd_i16x8_saturate(AOTCompContext *comp_ctx,
is_signed ? intrinsics[arith_op][0]
: intrinsics[arith_op][1]);
}
bool
aot_compile_simd_i32x4_saturate(AOTCompContext *comp_ctx,
AOTFuncContext *func_ctx,
V128Arithmetic arith_op, bool is_signed)
{
char *intrinsics[][2] = {
{ "llvm.sadd.sat.v4i32", "llvm.uadd.sat.v4i32" },
{ "llvm.ssub.sat.v4i32", "llvm.usub.sat.v4i32" },
};
return simd_sat_int_arith(comp_ctx, func_ctx, V128_i16x8_TYPE,
is_signed ? intrinsics[arith_op][0]
: intrinsics[arith_op][1]);
}

4
core/iwasm/compilation/simd/simd_sat_int_arith.h
View File

@ -22,10 +22,6 @@ aot_compile_simd_i16x8_saturate(AOTCompContext *comp_ctx,
AOTFuncContext *func_ctx,
V128Arithmetic arith_op, bool is_signed);
bool
aot_compile_simd_i32x4_saturate(AOTCompContext *comp_ctx,
AOTFuncContext *func_ctx,
V128Arithmetic arith_op, bool is_signed);
#ifdef __cplusplus
} /* end of extern "C" */
#endif

10
core/iwasm/interpreter/wasm_loader.c
View File

@ -15129,13 +15129,6 @@ re_scan:
break;
}
case SIMD_i32x4_narrow_i64x2_s:
case SIMD_i32x4_narrow_i64x2_u:
{
POP2_AND_PUSH(VALUE_TYPE_V128, VALUE_TYPE_V128);
break;
}
case SIMD_i32x4_extend_low_i16x8_s:
case SIMD_i32x4_extend_high_i16x8_s:
case SIMD_i32x4_extend_low_i16x8_u:
@ -15162,7 +15155,6 @@ re_scan:
case SIMD_i32x4_max_s:
case SIMD_i32x4_max_u:
case SIMD_i32x4_dot_i16x8_s:
case SIMD_i32x4_avgr_u:
case SIMD_i32x4_extmul_low_i16x8_s:
case SIMD_i32x4_extmul_high_i16x8_s:
case SIMD_i32x4_extmul_low_i16x8_u:
@ -15226,7 +15218,6 @@ re_scan:
/* f32x4 operation */
case SIMD_f32x4_abs:
case SIMD_f32x4_neg:
case SIMD_f32x4_round:
case SIMD_f32x4_sqrt:
{
POP_AND_PUSH(VALUE_TYPE_V128, VALUE_TYPE_V128);
@ -15249,7 +15240,6 @@ re_scan:
/* f64x2 operation */
case SIMD_f64x2_abs:
case SIMD_f64x2_neg:
case SIMD_f64x2_round:
case SIMD_f64x2_sqrt:
{
POP_AND_PUSH(VALUE_TYPE_V128, VALUE_TYPE_V128);

20
core/iwasm/interpreter/wasm_opcode.h
View File

@ -593,8 +593,8 @@ typedef enum WASMSimdEXTOpcode {
/* placeholder = 0xa2 */
SIMD_i32x4_all_true = 0xa3,
SIMD_i32x4_bitmask = 0xa4,
SIMD_i32x4_narrow_i64x2_s = 0xa5,
SIMD_i32x4_narrow_i64x2_u = 0xa6,
/* placeholder = 0xa5 */
/* placeholder = 0xa6 */
SIMD_i32x4_extend_low_i16x8_s = 0xa7,
SIMD_i32x4_extend_high_i16x8_s = 0xa8,
SIMD_i32x4_extend_low_i16x8_u = 0xa9,
@ -603,19 +603,19 @@ typedef enum WASMSimdEXTOpcode {
SIMD_i32x4_shr_s = 0xac,
SIMD_i32x4_shr_u = 0xad,
SIMD_i32x4_add = 0xae,
SIMD_i32x4_add_sat_s = 0xaf,
SIMD_i32x4_add_sat_u = 0xb0,
/* placeholder = 0xaf */
/* placeholder = 0xb0 */
SIMD_i32x4_sub = 0xb1,
SIMD_i32x4_sub_sat_s = 0xb2,
SIMD_i32x4_sub_sat_u = 0xb3,
/* placeholder = 0xb4 */
/* placeholder = 0xb2 */
/* placeholder = 0xb3 */
/* placeholder = 0xb4 */
SIMD_i32x4_mul = 0xb5,
SIMD_i32x4_min_s = 0xb6,
SIMD_i32x4_min_u = 0xb7,
SIMD_i32x4_max_s = 0xb8,
SIMD_i32x4_max_u = 0xb9,
SIMD_i32x4_dot_i16x8_s = 0xba,
SIMD_i32x4_avgr_u = 0xbb,
/* placeholder = 0xbb */
SIMD_i32x4_extmul_low_i16x8_s = 0xbc,
SIMD_i32x4_extmul_high_i16x8_s = 0xbd,
SIMD_i32x4_extmul_low_i16x8_u = 0xbe,
@ -658,7 +658,7 @@ typedef enum WASMSimdEXTOpcode {
/* f32x4 operation */
SIMD_f32x4_abs = 0xe0,
SIMD_f32x4_neg = 0xe1,
SIMD_f32x4_round = 0xe2,
/* placeholder = 0xe2 */
SIMD_f32x4_sqrt = 0xe3,
SIMD_f32x4_add = 0xe4,
SIMD_f32x4_sub = 0xe5,
@ -672,7 +672,7 @@ typedef enum WASMSimdEXTOpcode {
/* f64x2 operation */
SIMD_f64x2_abs = 0xec,
SIMD_f64x2_neg = 0xed,
SIMD_f64x2_round = 0xee,
/* placeholder = 0xee */
SIMD_f64x2_sqrt = 0xef,
SIMD_f64x2_add = 0xf0,
SIMD_f64x2_sub = 0xf1,