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Fix Zifencei extension issue in RISC-V (#2807)

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Refer to:
https://github.com/bytecodealliance/wasm-micro-runtime/pull/2805
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Huang Qi 2023-11-23 10:23:33 +08:00 committed by GitHub
parent 2175910bac
commit cb44e56b4e
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core/iwasm/aot/arch/aot_reloc_riscv.c
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@ -177,7 +177,11 @@ rv_set_val(uint16 *addr, uint32 val)
*addr = (val & 0xffff); *addr = (val & 0xffff);
*(addr + 1) = (val >> 16); *(addr + 1) = (val >> 16);
#ifdef __riscv_zifencei
__asm__ volatile("fence.i"); __asm__ volatile("fence.i");
#else
__asm__ volatile("fence");
#endif
} }
/* Add a val to given address */ /* Add a val to given address */