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NuttX: Replace esp32s3 bits with the OS-provided APIs (#3439)

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Expected merge order:
https://github.com/apache/nuttx/pull/12355
https://github.com/apache/nuttx-apps/pull/2395
https://github.com/bytecodealliance/wasm-micro-runtime/pull/3439
This commit is contained in:
YAMAMOTO Takashi 2024-05-18 21:35:16 +09:00 committed by GitHub
parent 7744e84607
commit ec44f494cc
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GPG Key ID: B5690EEEBB952194
1 changed files with 10 additions and 80 deletions
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90
core/shared/platform/nuttx/nuttx_platform.c
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@ -10,51 +10,6 @@
#include <nuttx/arch.h>
#endif
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
/*
* TODO: Move these methods below the operating system level
*/
#define MEM_DUAL_BUS_OFFSET (0x42000000 - 0x3C000000)
#define IRAM0_CACHE_ADDRESS_LOW 0x42000000
#define IRAM0_CACHE_ADDRESS_HIGH 0x44000000
#define IRAM_ATTR locate_data(".iram1")
#define INTERNAL_SRAM_1_DBUS_ADDRESS_LOW 0x3fc88000
#define INTERNAL_SRAM_1_DBUS_ADDRESS_HIGH 0x3fcf0000
#define INTERNAL_SRAM_1_IBUS_ADDRESS_LOW 0x40378000
#define INTERNAL_SRAM_1_IBUS_ADDRESS_HIGH 0x403e0000
#define in_ibus_ext(addr) \
(((uint32)addr >= IRAM0_CACHE_ADDRESS_LOW) \
&& ((uint32)addr < IRAM0_CACHE_ADDRESS_HIGH))
void IRAM_ATTR
bus_sync(void)
{
extern void cache_writeback_all(void);
extern uint32_t Cache_Disable_ICache(void);
extern void Cache_Enable_ICache(uint32_t autoload);
irqstate_t flags;
uint32_t preload;
flags = enter_critical_section();
cache_writeback_all();
preload = Cache_Disable_ICache();
Cache_Enable_ICache(preload);
leave_critical_section(flags);
}
#else
#define MEM_DUAL_BUS_OFFSET (0)
#define IRAM0_CACHE_ADDRESS_LOW (0)
#define IRAM0_CACHE_ADDRESS_HIGH (0)
#define in_ibus_ext(addr) (0)
static void
bus_sync(void)
{}
#endif
int
bh_platform_init()
{
@ -93,9 +48,6 @@ void *
os_mmap(void *hint, size_t size, int prot, int flags, os_file_handle file)
{
void *p;
#if (WASM_MEM_DUAL_BUS_MIRROR != 0)
void *i_addr, *d_addr;
#endif
#if defined(CONFIG_ARCH_USE_TEXT_HEAP)
if ((prot & MMAP_PROT_EXEC) != 0) {
@ -110,20 +62,6 @@ os_mmap(void *hint, size_t size, int prot, int flags, os_file_handle file)
if ((uint64)size >= UINT32_MAX)
return NULL;
#if (WASM_MEM_DUAL_BUS_MIRROR != 0)
if ((prot & MMAP_PROT_EXEC) != 0) {
d_addr = malloc((uint32)size);
if (d_addr == NULL) {
return NULL;
}
i_addr = (void *)((uint8 *)d_addr + MEM_DUAL_BUS_OFFSET);
p = in_ibus_ext(i_addr) ? i_addr : d_addr;
if (p) {
memset(p, 0, size);
}
return p;
}
#endif
/* Note: aot_loader.c assumes that os_mmap provides large enough
* alignment for any data sections. Some sections like rodata.cst32
* actually require alignment larger than the natural alignment
@ -155,12 +93,6 @@ os_munmap(void *addr, size_t size)
}
#endif
#if (WASM_MEM_DUAL_BUS_MIRROR != 0)
if (in_ibus_ext(addr)) {
free((void *)((uint8 *)addr - MEM_DUAL_BUS_OFFSET));
return;
}
#endif
free(addr);
}
@ -173,7 +105,10 @@ os_mprotect(void *addr, size_t size, int prot)
void
os_dcache_flush()
{
bus_sync();
#if defined(CONFIG_ARCH_USE_TEXT_HEAP) \
&& defined(CONFIG_ARCH_TEXT_HEAP_SEPARATE_DATA_ADDRESS)
up_textheap_data_sync();
#endif
}
void
@ -184,17 +119,12 @@ os_icache_flush(void *start, size_t len)
void *
os_get_dbus_mirror(void *ibus)
{
if (in_ibus_ext(ibus)) {
return (void *)((uint8 *)ibus - MEM_DUAL_BUS_OFFSET);
}
else if (INTERNAL_SRAM_1_IBUS_ADDRESS_LOW <= (uintptr_t)ibus
&& (uintptr_t)ibus < INTERNAL_SRAM_1_IBUS_ADDRESS_HIGH) {
return (void *)((uintptr_t)ibus - INTERNAL_SRAM_1_IBUS_ADDRESS_LOW
+ INTERNAL_SRAM_1_DBUS_ADDRESS_LOW);
}
else {
return ibus;
}
#if defined(CONFIG_ARCH_USE_TEXT_HEAP) \
&& defined(CONFIG_ARCH_TEXT_HEAP_SEPARATE_DATA_ADDRESS)
return up_textheap_data_address(ibus);
#else
return ibus;
#endif
}
#endif