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NuttX: Replace esp32s3 bits with the OS-provided APIs (#3439)
Expected merge order: https://github.com/apache/nuttx/pull/12355 https://github.com/apache/nuttx-apps/pull/2395 https://github.com/bytecodealliance/wasm-micro-runtime/pull/3439
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@ -10,51 +10,6 @@
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#include <nuttx/arch.h>
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#include <nuttx/arch.h>
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#endif
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#endif
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#if defined(CONFIG_ARCH_CHIP_ESP32S3)
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/*
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* TODO: Move these methods below the operating system level
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*/
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#define MEM_DUAL_BUS_OFFSET (0x42000000 - 0x3C000000)
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#define IRAM0_CACHE_ADDRESS_LOW 0x42000000
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#define IRAM0_CACHE_ADDRESS_HIGH 0x44000000
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#define IRAM_ATTR locate_data(".iram1")
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#define INTERNAL_SRAM_1_DBUS_ADDRESS_LOW 0x3fc88000
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#define INTERNAL_SRAM_1_DBUS_ADDRESS_HIGH 0x3fcf0000
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#define INTERNAL_SRAM_1_IBUS_ADDRESS_LOW 0x40378000
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#define INTERNAL_SRAM_1_IBUS_ADDRESS_HIGH 0x403e0000
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#define in_ibus_ext(addr) \
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(((uint32)addr >= IRAM0_CACHE_ADDRESS_LOW) \
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&& ((uint32)addr < IRAM0_CACHE_ADDRESS_HIGH))
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void IRAM_ATTR
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bus_sync(void)
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{
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extern void cache_writeback_all(void);
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extern uint32_t Cache_Disable_ICache(void);
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extern void Cache_Enable_ICache(uint32_t autoload);
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irqstate_t flags;
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uint32_t preload;
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flags = enter_critical_section();
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cache_writeback_all();
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preload = Cache_Disable_ICache();
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Cache_Enable_ICache(preload);
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leave_critical_section(flags);
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}
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#else
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#define MEM_DUAL_BUS_OFFSET (0)
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#define IRAM0_CACHE_ADDRESS_LOW (0)
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#define IRAM0_CACHE_ADDRESS_HIGH (0)
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#define in_ibus_ext(addr) (0)
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static void
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bus_sync(void)
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{}
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#endif
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int
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int
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bh_platform_init()
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bh_platform_init()
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{
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{
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@ -93,9 +48,6 @@ void *
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os_mmap(void *hint, size_t size, int prot, int flags, os_file_handle file)
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os_mmap(void *hint, size_t size, int prot, int flags, os_file_handle file)
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{
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{
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void *p;
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void *p;
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#if (WASM_MEM_DUAL_BUS_MIRROR != 0)
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void *i_addr, *d_addr;
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#endif
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#if defined(CONFIG_ARCH_USE_TEXT_HEAP)
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#if defined(CONFIG_ARCH_USE_TEXT_HEAP)
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if ((prot & MMAP_PROT_EXEC) != 0) {
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if ((prot & MMAP_PROT_EXEC) != 0) {
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@ -110,20 +62,6 @@ os_mmap(void *hint, size_t size, int prot, int flags, os_file_handle file)
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if ((uint64)size >= UINT32_MAX)
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if ((uint64)size >= UINT32_MAX)
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return NULL;
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return NULL;
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#if (WASM_MEM_DUAL_BUS_MIRROR != 0)
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if ((prot & MMAP_PROT_EXEC) != 0) {
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d_addr = malloc((uint32)size);
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if (d_addr == NULL) {
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return NULL;
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}
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i_addr = (void *)((uint8 *)d_addr + MEM_DUAL_BUS_OFFSET);
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p = in_ibus_ext(i_addr) ? i_addr : d_addr;
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if (p) {
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memset(p, 0, size);
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}
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return p;
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}
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#endif
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/* Note: aot_loader.c assumes that os_mmap provides large enough
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/* Note: aot_loader.c assumes that os_mmap provides large enough
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* alignment for any data sections. Some sections like rodata.cst32
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* alignment for any data sections. Some sections like rodata.cst32
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* actually require alignment larger than the natural alignment
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* actually require alignment larger than the natural alignment
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@ -155,12 +93,6 @@ os_munmap(void *addr, size_t size)
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}
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}
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#endif
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#endif
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#if (WASM_MEM_DUAL_BUS_MIRROR != 0)
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if (in_ibus_ext(addr)) {
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free((void *)((uint8 *)addr - MEM_DUAL_BUS_OFFSET));
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return;
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}
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#endif
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free(addr);
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free(addr);
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}
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}
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@ -173,7 +105,10 @@ os_mprotect(void *addr, size_t size, int prot)
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void
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void
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os_dcache_flush()
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os_dcache_flush()
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{
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{
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bus_sync();
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#if defined(CONFIG_ARCH_USE_TEXT_HEAP) \
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&& defined(CONFIG_ARCH_TEXT_HEAP_SEPARATE_DATA_ADDRESS)
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up_textheap_data_sync();
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#endif
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}
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}
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void
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void
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@ -184,17 +119,12 @@ os_icache_flush(void *start, size_t len)
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void *
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void *
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os_get_dbus_mirror(void *ibus)
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os_get_dbus_mirror(void *ibus)
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{
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{
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if (in_ibus_ext(ibus)) {
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#if defined(CONFIG_ARCH_USE_TEXT_HEAP) \
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return (void *)((uint8 *)ibus - MEM_DUAL_BUS_OFFSET);
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&& defined(CONFIG_ARCH_TEXT_HEAP_SEPARATE_DATA_ADDRESS)
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}
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return up_textheap_data_address(ibus);
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else if (INTERNAL_SRAM_1_IBUS_ADDRESS_LOW <= (uintptr_t)ibus
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#else
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&& (uintptr_t)ibus < INTERNAL_SRAM_1_IBUS_ADDRESS_HIGH) {
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return ibus;
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return (void *)((uintptr_t)ibus - INTERNAL_SRAM_1_IBUS_ADDRESS_LOW
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#endif
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+ INTERNAL_SRAM_1_DBUS_ADDRESS_LOW);
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}
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else {
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return ibus;
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}
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}
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}
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#endif
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#endif
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