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https://github.com/bytecodealliance/wasm-micro-runtime.git
synced 2025-02-06 06:55:07 +00:00
Bring up WAMR on esp32-s3 device (#2348)
esp32-s3's instruction memory and data memory can be accessed through mutual mirroring way, so we define a new feature named as WASM_MEM_DUAL_BUS_MIRROR.
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@ -461,4 +461,15 @@
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#define WASM_CONFIGURABLE_BOUNDS_CHECKS 0
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#endif
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/* Some chip cannot support external ram with rwx attr at the same time,
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it has to map it into 2 spaces of idbus and dbus, code in dbus can be
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read/written and read/executed in ibus. so there are 2 steps to execute
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the code, first, copy&do relocaiton in dbus space, and second execute
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it in ibus space, since in the 2 spaces the contents are the same,
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so we call it bus mirror.
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*/
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#ifndef WASM_MEM_DUAL_BUS_MIRROR
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#define WASM_MEM_DUAL_BUS_MIRROR 0
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#endif
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#endif /* end of _CONFIG_H_ */
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@ -3013,6 +3013,9 @@ create_sections(AOTModule *module, const uint8 *buf, uint32 size,
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uint32 section_size;
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uint64 total_size;
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uint8 *aot_text;
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#if (WASM_MEM_DUAL_BUS_MIRROR != 0)
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uint8 *mirrored_text;
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#endif
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if (!resolve_execute_mode(buf, size, &is_indirect_mode, error_buf,
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error_buf_size)) {
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@ -3071,8 +3074,17 @@ create_sections(AOTModule *module, const uint8 *buf, uint32 size,
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bh_assert((uintptr_t)aot_text < INT32_MAX);
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#endif
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#endif
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#if (WASM_MEM_DUAL_BUS_MIRROR != 0)
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mirrored_text = os_get_dbus_mirror(aot_text);
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bh_assert(mirrored_text != NULL);
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bh_memcpy_s(mirrored_text, (uint32)total_size,
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section->section_body, (uint32)section_size);
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os_dcache_flush();
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#else
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bh_memcpy_s(aot_text, (uint32)total_size,
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section->section_body, (uint32)section_size);
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#endif
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section->section_body = aot_text;
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destroy_aot_text = true;
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@ -207,6 +207,10 @@ apply_relocation(AOTModule *module, uint8 *target_section_addr,
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case R_XTENSA_32:
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{
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uint8 *insn_addr = target_section_addr + reloc_offset;
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#if (WASM_MEM_DUAL_BUS_MIRROR != 0)
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insn_addr = os_get_dbus_mirror((void *)insn_addr);
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bh_assert(insn_addr != NULL);
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#endif
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int32 initial_addend;
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/* (S + A) */
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if ((intptr_t)insn_addr & 3) {
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@ -265,6 +269,11 @@ apply_relocation(AOTModule *module, uint8 *target_section_addr,
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return false;
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}
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#if (WASM_MEM_DUAL_BUS_MIRROR != 0)
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insn_addr = os_get_dbus_mirror((void *)insn_addr);
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bh_assert(insn_addr != NULL);
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l32r_insn = (l32r_insn_t *)insn_addr;
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#endif
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imm16 = (int16)(relative_offset >> 2);
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/* write back the imm16 to the l32r instruction */
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@ -285,7 +294,6 @@ apply_relocation(AOTModule *module, uint8 *target_section_addr,
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#if __GNUC__ >= 9
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#pragma GCC diagnostic pop
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#endif
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break;
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}
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@ -129,6 +129,11 @@ os_munmap(void *addr, size_t size);
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int
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os_mprotect(void *addr, size_t size, int prot);
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#if (WASM_MEM_DUAL_BUS_MIRROR != 0)
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void *
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os_get_dbus_mirror(void *ibus);
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#endif
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/**
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* Flush cpu data cache, in some CPUs, after applying relocation to the
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* AOT code, the code may haven't been written back to the cpu data cache,
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@ -10,6 +10,46 @@
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#include <nuttx/arch.h>
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#endif
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#if defined(CONFIG_ARCH_CHIP_ESP32S3)
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/*
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* TODO: Move these methods below the operating system level
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*/
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#define MEM_DUAL_BUS_OFFSET (0x42000000 - 0x3C000000)
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#define IRAM0_CACHE_ADDRESS_LOW 0x42000000
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#define IRAM0_CACHE_ADDRESS_HIGH 0x44000000
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#define IRAM_ATTR locate_data(".iram1")
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#define in_ibus_ext(addr) \
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(((uint32)addr >= IRAM0_CACHE_ADDRESS_LOW) \
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&& ((uint32)addr < IRAM0_CACHE_ADDRESS_HIGH))
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void IRAM_ATTR
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bus_sync(void)
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{
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extern void cache_writeback_all(void);
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extern uint32_t Cache_Disable_ICache(void);
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extern void Cache_Enable_ICache(uint32_t autoload);
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irqstate_t flags;
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uint32_t preload;
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flags = enter_critical_section();
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cache_writeback_all();
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preload = Cache_Disable_ICache();
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Cache_Enable_ICache(preload);
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leave_critical_section(flags);
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}
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#else
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#define MEM_DUAL_BUS_OFFSET (0)
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#define IRAM0_CACHE_ADDRESS_LOW (0)
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#define IRAM0_CACHE_ADDRESS_HIGH (0)
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#define in_ibus_ext(addr) (0)
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static void
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bus_sync(void)
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{}
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#endif
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int
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bh_platform_init()
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{
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@ -47,6 +87,10 @@ os_dumps_proc_mem_info(char *out, unsigned int size)
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void *
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os_mmap(void *hint, size_t size, int prot, int flags)
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{
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#if (WASM_MEM_DUAL_BUS_MIRROR != 0)
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void *i_addr, *d_addr;
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#endif
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#if defined(CONFIG_ARCH_USE_TEXT_HEAP)
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if ((prot & MMAP_PROT_EXEC) != 0) {
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return up_textheap_memalign(sizeof(void *), size);
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@ -55,6 +99,17 @@ os_mmap(void *hint, size_t size, int prot, int flags)
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if ((uint64)size >= UINT32_MAX)
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return NULL;
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#if (WASM_MEM_DUAL_BUS_MIRROR != 0)
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if ((prot & MMAP_PROT_EXEC) != 0) {
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d_addr = malloc((uint32)size);
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if (d_addr == NULL) {
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return NULL;
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}
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i_addr = (void *)((uint8 *)d_addr + MEM_DUAL_BUS_OFFSET);
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return in_ibus_ext(i_addr) ? i_addr : d_addr;
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}
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#endif
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return malloc((uint32)size);
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}
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@ -67,7 +122,14 @@ os_munmap(void *addr, size_t size)
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return;
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}
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#endif
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return free(addr);
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#if (WASM_MEM_DUAL_BUS_MIRROR != 0)
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if (in_ibus_ext(addr)) {
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free((void *)((uint8 *)addr - MEM_DUAL_BUS_OFFSET));
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return;
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}
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#endif
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free(addr);
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}
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int
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@ -78,7 +140,22 @@ os_mprotect(void *addr, size_t size, int prot)
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void
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os_dcache_flush()
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{}
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{
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bus_sync();
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}
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#if (WASM_MEM_DUAL_BUS_MIRROR != 0)
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void *
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os_get_dbus_mirror(void *ibus)
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{
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if (in_ibus_ext(ibus)) {
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return (void *)((uint8 *)ibus - MEM_DUAL_BUS_OFFSET);
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}
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else {
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return ibus;
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}
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}
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#endif
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/* If AT_FDCWD is provided, maybe we have openat family */
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#if !defined(AT_FDCWD)
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@ -141,6 +141,12 @@ else
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CFLAGS += -DWASM_ENABLE_WORD_ALIGN_READ=0
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endif
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ifeq ($(CONFIG_INTERPRETERS_WAMR_MEM_DUAL_BUS_MIRROR),y)
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CFLAGS += -DWASM_MEM_DUAL_BUS_MIRROR=1
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else
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CFLAGS += -DWASM_MEM_DUAL_BUS_MIRROR=0
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endif
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ifeq ($(CONFIG_INTERPRETERS_WAMR_FAST), y)
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CFLAGS += -DWASM_ENABLE_FAST_INTERP=1
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CFLAGS += -DWASM_ENABLE_INTERP=1
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