7 Commits

Author	SHA1	Message	Date
Wenyong Huang	327374cfee	Fix some compile warnings and typos (#3854) ... - Clear some compile warnings - Fix some typos - Fix llvm LICENSE link error - Remove unused aot file and binarydump bin - Add checks when loading AOT exports	2024-10-15 16:04:58 +08:00
Wenyong Huang	9ba36e284c	Implement shared heap for AOT (#3815)	2024-09-29 12:50:59 +08:00
WenLY1	4dacef2d60	shared heap: Fix some issues and add basic unit test case (#3801) ... Fix some issues and add basic unit test case for shared heap feature. Signed-off-by: wenlingyun1 <wenlingyun1@xiaomi.com>	2024-09-20 14:24:38 +08:00
Marcin Kolny	37d7439ef9	[refactoring] Extract read leb to a separate file, share the code between loader and mini loader (#3701) ... There's probably a number of other places where the bh_leb_read could be used (e.g. aot loader) but I'm making the change as small as possible. Further refactoring can be done later.	2024-08-14 08:46:24 +08:00
YAMAMOTO Takashi	4c2af25aff	aot compiler: Use larger alignment for load/store when possible (#3552) ... Consider the following wasm module: ```wast (module (func (export "foo") i32.const 0x104 i32.const 0x12345678 i32.store ) (memory 1 1) ) ``` While the address (0x104) is perfectly aligned for i32.store, as our aot compiler uses 1-byte alignment for load/store LLVM IR instructions, it often produces inefficient machine code, especially for alignment-sensitive targets. For example, the above "foo" function is compiled into the following xtensa machine code. ``` 0000002c <aot_func_internal#0>: 2c: 004136 entry a1, 32 2f: 07a182 movi a8, 0x107 32: 828a add.n a8, a2, a8 34: 291c movi.n a9, 18 36: 004892 s8i a9, a8, 0 39: 06a182 movi a8, 0x106 3c: 828a add.n a8, a2, a8 3e: ffff91 l32r a9, 3c <aot_func_internal#0+0x10> (ff91828a <aot_func_internal#0+0xff91825e>) 3e: R_XTENSA_SLOT0_OP .literal+0x8 41: 004892 s8i a9, a8, 0 44: 05a182 movi a8, 0x105 47: 828a add.n a8, a2, a8 49: ffff91 l32r a9, 48 <aot_func_internal#0+0x1c> (ffff9182 <aot_func_internal#0+0xffff9156>) 49: R_XTENSA_SLOT0_OP .literal+0xc 4c: 41a890 srli a10, a9, 8 4f: 0048a2 s8i a10, a8, 0 52: 04a182 movi a8, 0x104 55: 828a add.n a8, a2, a8 57: 004892 s8i a9, a8, 0 5a: f01d retw.n ``` Note that the each four bytes are stored separately using one-byte-store instruction, s8i. This commit tries to use larger alignments for load/store LLVM IR instructions when possible. with this commit, the above example is compiled into the following machine code, which seems more reasonable. ``` 0000002c <aot_func_internal#0>: 2c: 004136 entry a1, 32 2f: ffff81 l32r a8, 2c <aot_func_internal#0> (81004136 <aot_func_internal#0+0x8100410a>) 2f: R_XTENSA_SLOT0_OP .literal+0x8 32: 416282 s32i a8, a2, 0x104 35: f01d retw.n ``` Note: this doesn't work well for --xip because aot_load_const_from_table() hides the constness of the value. Maybe we need our own mechanism to propagate the constness and the value.	2024-06-22 10:32:52 +08:00
Zhang, Yi	380cd7b0e7	Add unit test suites (#3490)	2024-06-04 11:24:27 +08:00
Marcin Kolny	8c2dc1d011	Add unit tests for the tid allocator (#2519) ... Add simple infrastructure to add more unit tests in the future. At the moment tests are only executed on Linux, but can be extended to other platforms if needed. Use https://github.com/google/googletest/ as a framework.	2023-09-04 13:21:10 +08:00