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46472ee6c8
3 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
liang.he
|
46472ee6c8
|
Enable Unit test on Mac(m1) (#4841)
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spec test on nuttx / spec_test_on_qemu (map[config:boards/risc-v/qemu-rv/rv-virt/configs/nsh fpu_type:none target:riscv32], map[mode: option:], map[mode:-t aot option:CONFIG_INTERPRETERS_WAMR_AOT]) (push) Has been cancelled
spec test on nuttx / spec_test_on_qemu (map[config:boards/risc-v/qemu-rv/rv-virt/configs/nsh64 fpu_type:none target:riscv64], map[mode: option:], map[mode:-t aot -X option:CONFIG_INTERPRETERS_WAMR_AOT]) (push) Has been cancelled
spec test on nuttx / spec_test_on_qemu (map[config:boards/risc-v/qemu-rv/rv-virt/configs/nsh64 fpu_type:none target:riscv64], map[mode: option:], map[mode:-t aot option:CONFIG_INTERPRETERS_WAMR_AOT]) (push) Has been cancelled
spec test on nuttx / spec_test_on_qemu (map[config:boards/xtensa/esp32s3/esp32s3-devkit/configs/qemu_debug fpu_type:none target:xtensa], map[mode: option:], map[mode:-t aot -X option:CONFIG_INTERPRETERS_WAMR_AOT]) (push) Has been cancelled
spec test on nuttx / spec_test_on_qemu (map[config:boards/xtensa/esp32s3/esp32s3-devkit/configs/qemu_debug fpu_type:none target:xtensa], map[mode: option:], map[mode:-t aot option:CONFIG_INTERPRETERS_WAMR_AOT]) (push) Has been cancelled
- detecting host arch. and platform instead of hard-coding - fix few compilation errors because of stricter rules involve by appleclang - refactor: modernize wasm-apps CMakeLists.txt to target-specific options and install commands - refactor: modernize memory64 CMakeLists.txt to target-specific options and install commands - Update running-modes CMakeLists.txt: enable AOT and INTERP; JIT/FAST_JIT gating for x86_64. Fix typo in JIT section. - fix: replace deprecated get_binary_path function with get_test_binary_dir for improved portability - fix: adjust size_level test cases for aarch64 architecture compatibility |
||
|
YAMAMOTO Takashi
|
4c2af25aff
|
aot compiler: Use larger alignment for load/store when possible (#3552)
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Consider the following wasm module:
```wast
(module
(func (export "foo")
i32.const 0x104
i32.const 0x12345678
i32.store
)
(memory 1 1)
)
```
While the address (0x104) is perfectly aligned for i32.store,
as our aot compiler uses 1-byte alignment for load/store LLVM
IR instructions, it often produces inefficient machine code,
especially for alignment-sensitive targets.
For example, the above "foo" function is compiled into the
following xtensa machine code.
```
0000002c <aot_func_internal#0>:
2c: 004136 entry a1, 32
2f: 07a182 movi a8, 0x107
32: 828a add.n a8, a2, a8
34: 291c movi.n a9, 18
36: 004892 s8i a9, a8, 0
39: 06a182 movi a8, 0x106
3c: 828a add.n a8, a2, a8
3e: ffff91 l32r a9, 3c <aot_func_internal#0+0x10> (ff91828a <aot_func_internal#0+0xff91825e>)
3e: R_XTENSA_SLOT0_OP .literal+0x8
41: 004892 s8i a9, a8, 0
44: 05a182 movi a8, 0x105
47: 828a add.n a8, a2, a8
49: ffff91 l32r a9, 48 <aot_func_internal#0+0x1c> (ffff9182 <aot_func_internal#0+0xffff9156>)
49: R_XTENSA_SLOT0_OP .literal+0xc
4c: 41a890 srli a10, a9, 8
4f: 0048a2 s8i a10, a8, 0
52: 04a182 movi a8, 0x104
55: 828a add.n a8, a2, a8
57: 004892 s8i a9, a8, 0
5a: f01d retw.n
```
Note that the each four bytes are stored separately using
one-byte-store instruction, s8i.
This commit tries to use larger alignments for load/store LLVM IR
instructions when possible. with this commit, the above example is
compiled into the following machine code, which seems more reasonable.
```
0000002c <aot_func_internal#0>:
2c: 004136 entry a1, 32
2f: ffff81 l32r a8, 2c <aot_func_internal#0> (81004136 <aot_func_internal#0+0x8100410a>)
2f: R_XTENSA_SLOT0_OP .literal+0x8
32: 416282 s32i a8, a2, 0x104
35: f01d retw.n
```
Note: this doesn't work well for --xip because aot_load_const_from_table()
hides the constness of the value. Maybe we need our own mechanism to
propagate the constness and the value.
|
||
|
Zhang, Yi
|
380cd7b0e7
|
Add unit test suites (#3490) |