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5cead96efc
8 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
liang.he
|
5cead96efc
|
Merge branch main into dev/zephyr_file_socket (#4531)
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compilation on SGX / run_samples_file (-DWAMR_BUILD_SGX_IPFS=1, $FAST_INTERP_BUILD_OPTIONS, ${{ needs.build_llvm_libraries.outputs.cache_key }}, ubuntu-22.04, linux-sgx) (push) Blocked by required conditions
compilation on SGX / run_samples_file (-DWAMR_BUILD_SGX_IPFS=1, $FAST_JIT_BUILD_OPTIONS, ${{ needs.build_llvm_libraries.outputs.cache_key }}, ubuntu-22.04, linux-sgx) (push) Blocked by required conditions
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hadolint dockerfiles / run-hadolint-on-dockerfiles (push) Has been cancelled
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|
TianlongLiang
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f2b87d773e
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Support external toolchain on Windows for aot compiler (#3911)
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allowing custom ARC toolchain on Windows |
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Cengizhan Pasaoglu
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81fbfbfcc0
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Remove unnecessary and extra zero length check in mem functions' macro (#2428)
In macro bh_memcpy_s, bh_memcy_wa and bh_memmove_s, no need to do extra check for length is zero or not because it was already done inside of the functions called. |
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dongsheng28849455
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e517dbc7b2
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XIP adaptation for xtensa platform (#1636)
Add macro WASM_ENABLE_WORD_ALING_READ to enable reading 1/2/4 and n bytes data from vram buffer, which requires 4-byte addr alignment reading. Eliminate XIP AOT relocations related to the below ones: i32_div_u, f32_min, f32_max, f32_ceil, f32_floor, f32_trunc, f32_rint |
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Wenyong Huang
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d62543c99c
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Enlarge max pool size and fix bh_memcpy_s dest max size check (#1151)
Enlarge max pool size and fix bh_memcpy_s dest max size check to support large linear memory, e.g. with initial page count 65535. |
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Wenyong Huang
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17f62ad472
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Apply clang-format for core/shared and product-mini files (#785)
Apply clang-format for core/shared and product-mini files |
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wenyongh
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752826a667
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Implement multi-module feature and bulk-memory feature (#271)
Refine wasm loader and aot loader Fix potential issue of os_mmap/os_munmap Update document |
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Xu Jun
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f1a0e75ab7
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re-org platform APIs, simplify porting process (#201)
Co-authored-by: Xu Jun <jun1.xu@intel.com> |