Commit Graph

25 Commits

Author SHA1 Message Date
Wenyong Huang
9e3c6acb25
Fix fast jit issues (#1193)
And implement several opcodes
2022-05-30 15:27:22 +08:00
liang.he
b01ae11217
Implement float comparison, conversion and numeric opcodes (#1170) 2022-05-24 19:03:46 +08:00
Wenyong Huang
e675564381
Fix fast jit issues (#1169)
Implement bitwise 64-bit operations in codegen
Fix and refine shift IRs
Zero local variables
Remove ref-type/bulk-memory macros
Implement set aux stack
Refine clear mem registers
2022-05-16 15:17:48 +08:00
liang.he
eec5450d26
Implement fast jit float/double load/store opcodes translation (#1165) 2022-05-10 17:23:53 +08:00
Wenyong Huang
4135622008
Fix fast jit several issues (#1163) 2022-05-10 15:22:43 +08:00
liang.he
dd966977a5
Implement JIT IR translation for opcode call_indirect (#1138) 2022-05-06 15:31:21 +08:00
liang.he
87b259a40a
Implement opcode memory.grow and fix zydis compile error (#1123) 2022-04-27 20:02:38 +08:00
liang.he
26c4a7ca33
Only handle one const case in DEF_UNI_INT_CONST_OPS (#1122)
`DEF_UNI_INT_CONST_OPS` handle the case of both consts
2022-04-26 15:59:15 +08:00
liang.he
0377aec027
Emit JIT IRs for wasm opcode ROTL and ROTR (#1114) 2022-04-24 13:50:27 +08:00
liang.he
ab5eaef5b8
Implement I64_EXTEND_I32 and I32_WRAP_I64 for Fast JIT (#1111) 2022-04-21 18:15:56 +08:00
liang.he
0c2cac4ca2
Emit JIT IR for bitwise opcodes (#1101) 2022-04-21 17:48:24 +08:00
liang.he
94d6da28b7
Emit JIT IR for wasm opcode SHL/SHRU/SHRS (#1097) 2022-04-19 16:24:37 +08:00
liang.he
166f12fef1
Implement JIT IR for integer load/store opcodes (#1087) 2022-04-18 17:22:55 +08:00
Wenyong Huang
5f0fab03a5
Implement i32/i64 div and rem opcodes translation (#1091) 2022-04-18 11:38:10 +08:00
liang.he
f1f674bc8d
Emit JIT IRs for get/set wasm globals (#1085)
WASM_OP_SET_GLOBAL_AUX_STACK is unsupported currently
2022-04-14 14:07:37 +08:00
liang.he
8ef253a19c
Emit JIT IR for integer comparison (#1086) 2022-04-13 13:43:45 +08:00
Wenyong Huang
27446e4b14
Implement load fixed virtual regs (#1083) 2022-04-12 14:54:38 +08:00
Wenyong Huang
d4fe9fcbdc
Add pointer reg and LDPTR/STPTR to refine the code (#1079)
And define the fixed virtual registers, create them at the beginning.
2022-04-12 09:01:08 +08:00
Wenyong Huang
3b7bc63274
Implement op_call for fast-jit (#1075)
Translate WASM_OP_CALL into JIT IR in the frontend, and translate
JIT_OP_CALLBC and JIT_OP_CALLNATIVE in the backend.
For calling wasm native API, simply call wasm_interp_call_func_native
to reduce the complexity.
And fix some issues, including wasm loader, frontend, register allocator,
and code gen.
2022-04-10 18:41:23 +08:00
liang.he
4d966d45ee
Fix issues of compiling control related opcodes (#1063) 2022-04-03 20:25:13 +08:00
liang.he
8113536278
Implement IR translation of BR_TABLE (#1064)
And refine IR translation of BR_IF
2022-04-02 14:02:06 +08:00
Wenyong Huang
f7b6cd75c7
Implement part of codegen, add asmjit and zydis (#1050)
Implement part of codegen and fix some frontend issues
Add asmjit to emit native code and add zydis to disassemble native code
Can successfully run some simple cases
2022-03-22 12:22:04 +08:00
liang.he
0f2885cd66
Fix issues of handling op block/if/loop/else (#1049)
Since `basic_block_else` is NULL, it meets a crash if there is a
IF block without a else branch. Like:

``` wat
(func (export "params-id") (param i32) (result i32)
  (i32.const 1)
  (if (param i32) (result i32) (local.get 0)
    (then)
  )
)
```

Consider the ELSE block will be created lazily, focus on
`basic_block_entry" here.
2022-03-21 14:00:58 +08:00
Wenyong Huang
eb518c0423
Refine code, fix some issues and add codegen framework (#1045)
Add more return value checks and set lass error
Implement exception throw and add operand stack overflow check
Remove lower_fe pass
Use cc->cmp_reg for cmp/branch IRs
Fix jit dump issues
Fix some compile warnings
Add part of codegen framework
Remove some unused JIT IRs
2022-03-14 15:32:32 +08:00
Wenyong Huang
24aae4f0d6
Import Fast JIT framework (#1016)
Import Fast JIT framework and translate some opcodes in the frontend.
2022-03-09 12:34:56 +08:00