mirror of
https://github.com/bytecodealliance/wasm-micro-runtime.git
synced 2025-02-06 15:05:19 +00:00
7e9bf9cdf5
- Translate all the opcodes of threads spec proposal for Fast JIT - Add the atomic flag for Fast JIT load/store IRs to support atomic load/store - Add new atomic related Fast JIT IRs and translate them in the codegen - Add suspend_flags check in branch opcodes and before/after call function - Modify CI to enable Fast JIT multi-threading test Co-authored-by: TianlongLiang <tianlong.liang@intel.com>
337 lines
8.9 KiB
C
337 lines
8.9 KiB
C
/*
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* Copyright (C) 2021 Intel Corporation. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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*/
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#include "jit_dump.h"
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#include "jit_compiler.h"
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#include "jit_codegen.h"
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void
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jit_dump_reg(JitCompContext *cc, JitReg reg)
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{
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unsigned kind = jit_reg_kind(reg);
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unsigned no = jit_reg_no(reg);
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switch (kind) {
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case JIT_REG_KIND_VOID:
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os_printf("VOID");
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break;
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case JIT_REG_KIND_I32:
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if (jit_reg_is_const(reg)) {
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unsigned rel = jit_cc_get_const_I32_rel(cc, reg);
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os_printf("0x%x", jit_cc_get_const_I32(cc, reg));
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if (rel)
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os_printf("(rel: 0x%x)", rel);
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}
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else
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os_printf("i%d", no);
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break;
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case JIT_REG_KIND_I64:
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if (jit_reg_is_const(reg))
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os_printf("0x%llxL", jit_cc_get_const_I64(cc, reg));
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else
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os_printf("I%d", no);
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break;
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case JIT_REG_KIND_F32:
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if (jit_reg_is_const(reg))
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os_printf("%f", jit_cc_get_const_F32(cc, reg));
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else
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os_printf("f%d", no);
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break;
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case JIT_REG_KIND_F64:
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if (jit_reg_is_const(reg))
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os_printf("%fL", jit_cc_get_const_F64(cc, reg));
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else
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os_printf("D%d", no);
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break;
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case JIT_REG_KIND_L32:
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os_printf("L%d", no);
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break;
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default:
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bh_assert(!"Unsupported register kind.");
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}
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}
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static void
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jit_dump_insn_Reg(JitCompContext *cc, JitInsn *insn, unsigned opnd_num)
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{
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unsigned i;
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for (i = 0; i < opnd_num; i++) {
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os_printf(i == 0 ? " " : ", ");
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jit_dump_reg(cc, *(jit_insn_opnd(insn, i)));
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}
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os_printf("\n");
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}
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static void
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jit_dump_insn_VReg(JitCompContext *cc, JitInsn *insn, unsigned opnd_num)
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{
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unsigned i;
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opnd_num = jit_insn_opndv_num(insn);
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for (i = 0; i < opnd_num; i++) {
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os_printf(i == 0 ? " " : ", ");
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jit_dump_reg(cc, *(jit_insn_opndv(insn, i)));
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}
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os_printf("\n");
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}
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static void
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jit_dump_insn_LookupSwitch(JitCompContext *cc, JitInsn *insn, unsigned opnd_num)
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{
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unsigned i;
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JitOpndLookupSwitch *opnd = jit_insn_opndls(insn);
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os_printf(" ");
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jit_dump_reg(cc, opnd->value);
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os_printf("\n%16s: ", "default");
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jit_dump_reg(cc, opnd->default_target);
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os_printf("\n");
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for (i = 0; i < opnd->match_pairs_num; i++) {
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os_printf("%18d: ", opnd->match_pairs[i].value);
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jit_dump_reg(cc, opnd->match_pairs[i].target);
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os_printf("\n");
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}
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}
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void
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jit_dump_insn(JitCompContext *cc, JitInsn *insn)
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{
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switch (insn->opcode) {
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#define INSN(NAME, OPND_KIND, OPND_NUM, FIRST_USE) \
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case JIT_OP_##NAME: \
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if (insn->flags_u8 & 0x1) \
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os_printf(" ATOMIC %-8s", #NAME); \
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else \
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os_printf(" %-15s", #NAME); \
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jit_dump_insn_##OPND_KIND(cc, insn, OPND_NUM); \
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break;
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#include "jit_ir.def"
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#undef INSN
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}
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}
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void
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jit_dump_basic_block(JitCompContext *cc, JitBasicBlock *block)
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{
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unsigned i, label_index;
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void *begin_addr, *end_addr;
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JitBasicBlock *block_next;
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JitInsn *insn;
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JitRegVec preds = jit_basic_block_preds(block);
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JitRegVec succs = jit_basic_block_succs(block);
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JitReg label = jit_basic_block_label(block), label_next;
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JitReg *reg;
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jit_dump_reg(cc, label);
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os_printf(":\n ; PREDS(");
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JIT_REG_VEC_FOREACH(preds, i, reg)
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{
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if (i > 0)
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os_printf(" ");
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jit_dump_reg(cc, *reg);
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}
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os_printf(")\n ;");
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if (jit_annl_is_enabled_begin_bcip(cc))
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os_printf(" BEGIN_BCIP=0x%04tx",
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*(jit_annl_begin_bcip(cc, label))
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- (uint8 *)cc->cur_wasm_module->load_addr);
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if (jit_annl_is_enabled_end_bcip(cc))
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os_printf(" END_BCIP=0x%04tx",
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*(jit_annl_end_bcip(cc, label))
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- (uint8 *)cc->cur_wasm_module->load_addr);
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os_printf("\n");
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if (jit_annl_is_enabled_jitted_addr(cc)) {
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begin_addr = *(jit_annl_jitted_addr(cc, label));
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if (label == cc->entry_label) {
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block_next = cc->_ann._label_basic_block[2];
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label_next = jit_basic_block_label(block_next);
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end_addr = *(jit_annl_jitted_addr(cc, label_next));
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}
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else if (label == cc->exit_label) {
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end_addr = cc->jitted_addr_end;
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}
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else {
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label_index = jit_reg_no(label);
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if (label_index < jit_cc_label_num(cc) - 1)
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block_next = cc->_ann._label_basic_block[label_index + 1];
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else
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block_next = cc->_ann._label_basic_block[1];
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label_next = jit_basic_block_label(block_next);
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end_addr = *(jit_annl_jitted_addr(cc, label_next));
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}
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jit_codegen_dump_native(begin_addr, end_addr);
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}
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else {
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/* Dump IR. */
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JIT_FOREACH_INSN(block, insn) jit_dump_insn(cc, insn);
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}
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os_printf(" ; SUCCS(");
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JIT_REG_VEC_FOREACH(succs, i, reg)
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{
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if (i > 0)
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os_printf(" ");
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jit_dump_reg(cc, *reg);
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}
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os_printf(")\n\n");
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}
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static void
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dump_func_name(JitCompContext *cc)
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{
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const char *func_name = NULL;
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WASMModule *module = cc->cur_wasm_module;
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#if WASM_ENABLE_CUSTOM_NAME_SECTION != 0
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func_name = cc->cur_wasm_func->field_name;
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#endif
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/* if custom name section is not generated,
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search symbols from export table */
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if (!func_name) {
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uint32 i;
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for (i = 0; i < module->export_count; i++) {
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if (module->exports[i].kind == EXPORT_KIND_FUNC
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&& module->exports[i].index == cc->cur_wasm_func_idx) {
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func_name = module->exports[i].name;
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break;
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}
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}
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}
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/* function name not exported, print number instead */
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if (func_name == NULL) {
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os_printf("$f%d", cc->cur_wasm_func_idx);
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}
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else {
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os_printf("%s", func_name);
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}
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}
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static void
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dump_cc_ir(JitCompContext *cc)
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{
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unsigned i, end;
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JitBasicBlock *block;
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JitReg label;
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const char *kind_names[] = { "VOID", "I32", "I64", "F32",
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"F64", "V64", "V128", "V256" };
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os_printf("; Function: ");
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dump_func_name(cc);
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os_printf("\n");
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os_printf("; Constant table sizes:");
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for (i = 0; i < JIT_REG_KIND_L32; i++)
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os_printf(" %s=%d", kind_names[i], cc->_const_val._num[i]);
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os_printf("\n; Label number: %d", jit_cc_label_num(cc));
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os_printf("\n; Instruction number: %d", jit_cc_insn_num(cc));
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os_printf("\n; Register numbers:");
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for (i = 0; i < JIT_REG_KIND_L32; i++)
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os_printf(" %s=%d", kind_names[i], jit_cc_reg_num(cc, i));
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os_printf("\n; Label annotations:");
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#define ANN_LABEL(TYPE, NAME) \
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if (jit_annl_is_enabled_##NAME(cc)) \
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os_printf(" %s", #NAME);
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#include "jit_ir.def"
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#undef ANN_LABEL
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os_printf("\n; Instruction annotations:");
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#define ANN_INSN(TYPE, NAME) \
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if (jit_anni_is_enabled_##NAME(cc)) \
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os_printf(" %s", #NAME);
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#include "jit_ir.def"
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#undef ANN_INSN
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os_printf("\n; Register annotations:");
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#define ANN_REG(TYPE, NAME) \
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if (jit_annr_is_enabled_##NAME(cc)) \
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os_printf(" %s", #NAME);
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#include "jit_ir.def"
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#undef ANN_REG
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os_printf("\n\n");
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if (jit_annl_is_enabled_next_label(cc)) {
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/* Blocks have been reordered, use that order to dump. */
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for (label = cc->entry_label; label;
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label = *(jit_annl_next_label(cc, label)))
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jit_dump_basic_block(cc, *(jit_annl_basic_block(cc, label)));
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}
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else {
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/* Otherwise, use the default order. */
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jit_dump_basic_block(cc, jit_cc_entry_basic_block(cc));
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JIT_FOREACH_BLOCK(cc, i, end, block) jit_dump_basic_block(cc, block);
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jit_dump_basic_block(cc, jit_cc_exit_basic_block(cc));
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}
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}
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void
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jit_dump_cc(JitCompContext *cc)
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{
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if (jit_cc_label_num(cc) <= 2)
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return;
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dump_cc_ir(cc);
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}
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bool
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jit_pass_dump(JitCompContext *cc)
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{
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const JitGlobals *jit_globals = jit_compiler_get_jit_globals();
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const uint8 *passes = jit_globals->passes;
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uint8 pass_no = cc->cur_pass_no;
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const char *pass_name =
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pass_no > 0 ? jit_compiler_get_pass_name(passes[pass_no - 1]) : "NULL";
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#if defined(BUILD_TARGET_X86_64) || defined(BUILD_TARGET_AMD_64)
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if (!strcmp(pass_name, "lower_cg"))
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/* Ignore lower codegen pass as it does nothing in x86-64 */
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return true;
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#endif
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os_printf("JIT.COMPILER.DUMP: PASS_NO=%d PREV_PASS=%s\n\n", pass_no,
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pass_name);
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jit_dump_cc(cc);
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os_printf("\n");
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return true;
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}
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bool
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jit_pass_update_cfg(JitCompContext *cc)
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{
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return jit_cc_update_cfg(cc);
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}
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