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https://github.com/bytecodealliance/wasm-micro-runtime.git
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e4023c8e02
Enable RISCV AOT support, the supported ABIs are LP64 and LP64D for riscv64, ILP32 and ILP32D for riscv32.
For wamrc:
use --target=riscv64/riscv32 to specify the target arch of output AOT file,
use --target-abi=lp64d/lp64/ilp32d/ilp32 to specify the target ABI,
if --target-abi isn't specified, by default lp64d is used for riscv64, and ilp32d is used for riscv32.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Co-authored-by: wenyongh <wenyong.huang@intel.com>
149 lines
5.4 KiB
ArmAsm
149 lines
5.4 KiB
ArmAsm
/*
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* Copyright (C) 2019 Intel Corporation. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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*/
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/*
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* The float abi macros used bellow are from risc-v c api:
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* https://github.com/riscv/riscv-c-api-doc/blob/master/riscv-c-api.md
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*
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*/
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#if defined(__riscv_float_abi_soft)
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#define RV_FPREG_SIZE 0
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#elif defined(__riscv_float_abi_single)
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#define RV_OP_LOADFPREG flw
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#define RV_OP_STROEFPREG fsw
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#define RV_FPREG_SIZE 4
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#elif defined(__riscv_float_abi_double)
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#define RV_OP_LOADFPREG fld
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#define RV_OP_STROEFPREG fsd
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#define RV_FPREG_SIZE 8
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#endif
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#if __riscv_xlen == 32
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#define RV_OP_LOADREG lw
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#define RV_OP_STOREREG sw
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#define RV_REG_SIZE 4
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#define RV_REG_SHIFT 2
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#define RV_FP_OFFSET (8 * RV_REG_SIZE)
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#define RV_INT_OFFSET 0
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#else
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#define RV_OP_LOADREG ld
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#define RV_OP_STOREREG sd
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#define RV_REG_SIZE 8
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#define RV_REG_SHIFT 3
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#define RV_FP_OFFSET 0
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#define RV_INT_OFFSET (8 * RV_FPREG_SIZE)
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#endif
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.text
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.align 2
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#ifndef BH_PLATFORM_DARWIN
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.globl invokeNative
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.type invokeNative, function
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invokeNative:
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#else
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.globl _invokeNative
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_invokeNative:
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#endif /* end of BH_PLATFORM_DARWIN */
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/*
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* Arguments passed in:
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*
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* a0 function ptr
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* a1 argv
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* a2 nstacks
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*/
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/*
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* sp (stack pointer)
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* |- sd/sw to store 64/32-bit values from register to memory
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* |- ld/lw to load from stack to register
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* fp/s0 (frame pointer)
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* a0-a7 (8 integer arguments)
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* |- sd/sw to store
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* |- ld/lw to load
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* fa0-a7 (8 float arguments)
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* |- fsd/fsw to store
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* |- fld/fsw to load
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* t0-t6 (temporaries regisgers)
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* |- caller saved
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*/
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/* reserve space on stack to save return address and frame pointer */
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addi sp, sp, - 2 * RV_REG_SIZE
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RV_OP_STOREREG fp, 0 * RV_REG_SIZE(sp) /* save frame pointer */
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RV_OP_STOREREG ra, 1 * RV_REG_SIZE(sp) /* save return address */
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mv fp, sp /* set frame pointer to bottom of fixed frame */
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/* save function ptr, argv & nstacks */
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mv t0, a0 /* t0 = function ptr */
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mv t1, a1 /* t1 = argv array address */
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mv t2, a2 /* t2 = nstack */
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#ifndef __riscv_float_abi_soft
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/* fill in fa0-7 float-registers*/
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RV_OP_LOADFPREG fa0, RV_FP_OFFSET + 0 * RV_FPREG_SIZE(t1) /* fa0 */
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RV_OP_LOADFPREG fa1, RV_FP_OFFSET + 1 * RV_FPREG_SIZE(t1) /* fa1 */
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RV_OP_LOADFPREG fa2, RV_FP_OFFSET + 2 * RV_FPREG_SIZE(t1) /* fa2 */
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RV_OP_LOADFPREG fa3, RV_FP_OFFSET + 3 * RV_FPREG_SIZE(t1) /* fa3 */
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RV_OP_LOADFPREG fa4, RV_FP_OFFSET + 4 * RV_FPREG_SIZE(t1) /* fa4 */
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RV_OP_LOADFPREG fa5, RV_FP_OFFSET + 5 * RV_FPREG_SIZE(t1) /* fa5 */
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RV_OP_LOADFPREG fa6, RV_FP_OFFSET + 6 * RV_FPREG_SIZE(t1) /* fa6 */
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RV_OP_LOADFPREG fa7, RV_FP_OFFSET + 7 * RV_FPREG_SIZE(t1) /* fa7 */
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#endif
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/* fill in a0-7 integer-registers*/
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RV_OP_LOADREG a0, RV_INT_OFFSET + 0 * RV_REG_SIZE(t1) /* a0 */
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RV_OP_LOADREG a1, RV_INT_OFFSET + 1 * RV_REG_SIZE(t1) /* a1 */
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RV_OP_LOADREG a2, RV_INT_OFFSET + 2 * RV_REG_SIZE(t1) /* a2 */
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RV_OP_LOADREG a3, RV_INT_OFFSET + 3 * RV_REG_SIZE(t1) /* a3 */
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RV_OP_LOADREG a4, RV_INT_OFFSET + 4 * RV_REG_SIZE(t1) /* a4 */
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RV_OP_LOADREG a5, RV_INT_OFFSET + 5 * RV_REG_SIZE(t1) /* a5 */
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RV_OP_LOADREG a6, RV_INT_OFFSET + 6 * RV_REG_SIZE(t1) /* a6 */
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RV_OP_LOADREG a7, RV_INT_OFFSET + 7 * RV_REG_SIZE(t1) /* a7 */
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/* t1 points to stack args */
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/* RV_FPREG_SIZE is zero when __riscv_float_abi_soft defined */
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addi t1, t1, RV_REG_SIZE * 8 + RV_FPREG_SIZE * 8
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/* directly call the function if no args in stack,
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x0 always holds 0 */
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beq t2, x0, call_func
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/* reserve enough stack space for function arguments */
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sll t3, t2, RV_REG_SHIFT /* shift left 3 bits. t3 = n_stacks * 8 */
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sub sp, sp, t3
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/* make 16-byte aligned */
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li t3, 15
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not t3, t3
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and sp, sp, t3
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/* save sp in t4 register */
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mv t4, sp
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/* copy left arguments from caller stack to own frame stack */
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loop_stack_args:
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beq t2, x0, call_func
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RV_OP_LOADREG t5, 0(t1) /* load stack argument, t5 = argv[i] */
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RV_OP_STOREREG t5, 0(t4) /* store t5 to reseved stack, sp[j] = t5 */
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addi t1, t1, RV_REG_SIZE /* move to next stack argument */
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addi t4, t4, RV_REG_SIZE /* move to next stack pointer */
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addi t2, t2, -1 /* decrease t2 every loop, nstacks = nstacks -1 */
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j loop_stack_args
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call_func:
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jalr t0
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/* restore registers pushed in stack or saved in another register */
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return:
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mv sp, fp /* restore sp saved in fp before function call */
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RV_OP_LOADREG fp, 0 * RV_REG_SIZE(sp) /* load previous frame poniter to fp register */
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RV_OP_LOADREG ra, 1 * RV_REG_SIZE(sp) /* load previous return address to ra register */
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addi sp, sp, 2 * RV_REG_SIZE /* pop frame, restore sp */
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jr ra
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