mirror of
https://github.com/bytecodealliance/wasm-micro-runtime.git
synced 2025-05-20 08:31:20 +00:00
c93508939a
In one instruction, if one or multiple operands tending to lock some hardware registers in IR phase, like EAX, EDX for DIV, ECX for SHIFT, it leads to two known cases. case 1: allocate VOID `SHRU i250,i249,i3`. if pr_3 was allocated to vr_249 first, incoming allocation of vr_3 leads a spill out of `vr_249` and clear the value of `vr->hreg` of vr_249. When applying allocation result in FOREACH in L732, a NULL will be assigned to. case 2: unexpected spill out `DIV_U i1,i1,i44`. if allocation of vr_44 needs to spill out one hardware register, there is a chance that `hr_4` will be selected. If it happens, codegen will operate EDX and overwrite vr_44 value. The reason of how `hr_4` will be spilled out is a hidden bug that both information of `rc->hreg[]` and `rc->vreg` can be transfered from one block to the next one. It means even there is no vr binds to a hr in current block, the hr may still be thought as a busy one becase of the left infroamtion of previous blocks Workaround for cases: - Add `MOV LOCKED_hr LOCKED_hr` just after the instruction. It prevents case 1 - Add `MOV LOCKED_hr LOCKED_hr` just before the instruction. It prevents case 2 |
||
|---|---|---|
| .. | ||
| cg | ||
| fe | ||
| iwasm_fast_jit.cmake | ||
| jit_codecache.c | ||
| jit_codecache.h | ||
| jit_codegen.c | ||
| jit_codegen.h | ||
| jit_compiler.c | ||
| jit_compiler.h | ||
| jit_dump.c | ||
| jit_dump.h | ||
| jit_frontend.c | ||
| jit_frontend.h | ||
| jit_ir.c | ||
| jit_ir.def | ||
| jit_ir.h | ||
| jit_regalloc.c | ||
| jit_utils.c | ||
| jit_utils.h | ||