Refine build script of zephyr product-mini, enable aot soft-float support (#188)

core/iwasm/aot/arch/aot_reloc_arm.c

@@ -44,6 +44,20 @@ void __aeabi_idivmod();
 void __aeabi_uidivmod();
 void __aeabi_ldivmod();
 void __aeabi_uldivmod();
+void __aeabi_i2d();
+void __aeabi_dadd();
+void __aeabi_ddiv();
+void __aeabi_dcmplt();
+void __aeabi_dcmpun();
+void __aeabi_dcmple();
+void __aeabi_dcmpge();
+void __aeabi_d2iz();
+void __aeabi_fcmplt();
+void __aeabi_fcmpun();
+void __aeabi_fcmple();
+void __aeabi_fcmpge();
+void __aeabi_f2iz();
+void __aeabi_f2d();
 
 static SymbolMap target_sym_map[] = {
     REG_COMMON_SYMBOLS,
@@ -77,7 +91,21 @@ static SymbolMap target_sym_map[] = {
     REG_SYM(__aeabi_idivmod),
     REG_SYM(__aeabi_uidivmod),
     REG_SYM(__aeabi_ldivmod),
-    REG_SYM(__aeabi_uldivmod)
+    REG_SYM(__aeabi_uldivmod),
+    REG_SYM(__aeabi_i2d),
+    REG_SYM(__aeabi_dadd),
+    REG_SYM(__aeabi_ddiv),
+    REG_SYM(__aeabi_dcmplt),
+    REG_SYM(__aeabi_dcmpun),
+    REG_SYM(__aeabi_dcmple),
+    REG_SYM(__aeabi_dcmpge),
+    REG_SYM(__aeabi_d2iz),
+    REG_SYM(__aeabi_fcmplt),
+    REG_SYM(__aeabi_fcmpun),
+    REG_SYM(__aeabi_fcmple),
+    REG_SYM(__aeabi_fcmpge),
+    REG_SYM(__aeabi_f2iz),
+    REG_SYM(__aeabi_f2d),
 };
 
 static void

core/iwasm/aot/arch/aot_reloc_thumb.c

@@ -43,6 +43,20 @@ void __aeabi_idivmod();
 void __aeabi_uidivmod();
 void __aeabi_ldivmod();
 void __aeabi_uldivmod();
+void __aeabi_i2d();
+void __aeabi_dadd();
+void __aeabi_ddiv();
+void __aeabi_dcmplt();
+void __aeabi_dcmpun();
+void __aeabi_dcmple();
+void __aeabi_dcmpge();
+void __aeabi_d2iz();
+void __aeabi_fcmplt();
+void __aeabi_fcmpun();
+void __aeabi_fcmple();
+void __aeabi_fcmpge();
+void __aeabi_f2iz();
+void __aeabi_f2d();
 
 static SymbolMap target_sym_map[] = {
     REG_COMMON_SYMBOLS,
@@ -76,7 +90,21 @@ static SymbolMap target_sym_map[] = {
     REG_SYM(__aeabi_idivmod),
     REG_SYM(__aeabi_uidivmod),
     REG_SYM(__aeabi_ldivmod),
-    REG_SYM(__aeabi_uldivmod)
+    REG_SYM(__aeabi_uldivmod),
+    REG_SYM(__aeabi_i2d),
+    REG_SYM(__aeabi_dadd),
+    REG_SYM(__aeabi_ddiv),
+    REG_SYM(__aeabi_dcmplt),
+    REG_SYM(__aeabi_dcmpun),
+    REG_SYM(__aeabi_dcmple),
+    REG_SYM(__aeabi_dcmpge),
+    REG_SYM(__aeabi_d2iz),
+    REG_SYM(__aeabi_fcmplt),
+    REG_SYM(__aeabi_fcmpun),
+    REG_SYM(__aeabi_fcmple),
+    REG_SYM(__aeabi_fcmpge),
+    REG_SYM(__aeabi_f2iz),
+    REG_SYM(__aeabi_f2d),
 };
 
 static void

core/iwasm/compilation/aot_emit_numberic.c

@@ -857,12 +857,33 @@ fail:
     return false;
 }
 
+static bool
+is_targeting_soft_float(LLVMTargetMachineRef target_machine)
+{
+    bool ret = false;
+    char *feature_string;
+
+    if (!(feature_string =
+                LLVMGetTargetMachineFeatureString(target_machine))) {
+        aot_set_last_error("llvm get target machine feature string fail.");
+        return false;
+    }
+
+    ret = strstr(feature_string, "+soft-float") ? true : false;
+    LLVMDisposeMessage(feature_string);
+    return ret;
+}
+
 static bool
 compile_op_float_arithmetic(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx,
                             FloatArithmetic arith_op, bool is_f32)
 {
     switch (arith_op) {
         case FLOAT_ADD:
+            if (is_targeting_soft_float(comp_ctx->target_machine))
+                DEF_FP_BINARY_OP(LLVMBuildFAdd(comp_ctx->builder, left, right, "fadd"),
+                                 "llvm build fadd fail.");
+            else
                 DEF_FP_BINARY_OP(call_llvm_float_expermental_constrained_intrinsic(
                                     comp_ctx,
                                     (is_f32
@@ -876,6 +897,10 @@ compile_op_float_arithmetic(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx,
                                  NULL);
             return true;
         case FLOAT_SUB:
+            if (is_targeting_soft_float(comp_ctx->target_machine))
+                DEF_FP_BINARY_OP(LLVMBuildFSub(comp_ctx->builder, left, right, "fsub"),
+                                 "llvm build fsub fail.");
+            else
                 DEF_FP_BINARY_OP(call_llvm_float_expermental_constrained_intrinsic(
                                     comp_ctx,
                                     (is_f32
@@ -889,6 +914,10 @@ compile_op_float_arithmetic(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx,
                                  NULL);
             return true;
         case FLOAT_MUL:
+            if (is_targeting_soft_float(comp_ctx->target_machine))
+                DEF_FP_BINARY_OP(LLVMBuildFMul(comp_ctx->builder, left, right, "fmul"),
+                                 "llvm build fmul fail.");
+            else
                 DEF_FP_BINARY_OP(call_llvm_float_expermental_constrained_intrinsic(
                                     comp_ctx,
                                     (is_f32
@@ -902,6 +931,10 @@ compile_op_float_arithmetic(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx,
                                  NULL);
             return true;
         case FLOAT_DIV:
+            if (is_targeting_soft_float(comp_ctx->target_machine))
+                DEF_FP_BINARY_OP(LLVMBuildFDiv(comp_ctx->builder, left, right, "fdiv"),
+                                 "llvm build fdiv fail.");
+            else
                 DEF_FP_BINARY_OP(call_llvm_float_expermental_constrained_intrinsic(
                                     comp_ctx,
                                     (is_f32
@@ -1017,6 +1050,14 @@ compile_op_float_math(AOTCompContext *comp_ctx, AOTFuncContext *func_ctx,
                             NULL);
             return true;
         case FLOAT_SQRT:
+            if (is_targeting_soft_float(comp_ctx->target_machine))
+                DEF_FP_UNARY_OP(call_llvm_float_math_intrinsic(comp_ctx,
+                                                   is_f32 ? "llvm.sqrt.f32" :
+                                                            "llvm.sqrt.f64",
+                                                   is_f32,
+                                                   operand),
+                                NULL);
+            else
                 DEF_FP_UNARY_OP(call_llvm_libm_expermental_constrained_intrinsic(
                                            comp_ctx,
                                            (is_f32

doc/build_wamr.md

@@ -155,18 +155,19 @@ cd zephyr/samples/
 cp -a <wamr_root_dir>/product-mini/platforms/zephyr/simple .
 cd simple
 ln -s <wamr_root_dir> wamr
-mkdir build && cd build
+source ../../zephyr-env.sh
-source ../../../zephyr-env.sh
-
-1. build for x86
-cmake -GNinja -DBOARD=qemu_x86_nommu ..
-ninja
-2. build for ARM
-modify ../prj.conf, modify the commented line "# CONFIG_ARM_MPU is not set" to "CONFIG_ARM_MPU=y"
-cmake -GNinja -DBOARD=nucleo_f767zi -DWAMR_BUILD_TARGET=THUMBV7 ..
-ninja
 
 ```
+
+1. build for x86 (qemu_x86_nommu)
+``` Bash
+./build.sh x86
+```
+2. build for ARM (nucleo_f767zi)
+``` Bash
+./build.sh stm32
+```
+
 Note:
 WAMR provides some features which can be easily configured by passing options to cmake, please see [Linux platform](./build_wamr.md#linux) for details. Currently in Zephyr, interpreter, AoT and builtin libc are enabled by default.
 

product-mini/platforms/linux/build_llvm.sh

@@ -1,6 +1,6 @@
 #!/bin/sh
 
-# Copyright (C) 2019 Intel Corporation. All rights reserved.
+# Copyright (C) 2020 Intel Corporation. All rights reserved.
 # SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 
 DEPS_DIR=${PWD}/../../../core/deps
@@ -8,7 +8,7 @@ DEPS_DIR=${PWD}/../../../core/deps
 cd ${DEPS_DIR}
 if [ ! -d "llvm" ]; then
   echo "Clone llvm to core/deps/ .."
-  git clone https://github.com/llvm-mirror/llvm.git
+  git clone --depth 1 https://github.com/llvm-mirror/llvm.git
 fi
 
 cd llvm

product-mini/platforms/zephyr/simple/build.sh

@@ -0,0 +1,35 @@
+#!/bin/bash
+
+# Copyright (C) 2019 Intel Corporation.  All rights reserved.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+X86_TARGET="x86"
+STM32_TARGET="stm32"
+
+if [ $# != 1 ] ; then
+        echo "USAGE:"
+        echo "$0 $X86_TARGET|$STM32_TARGET"
+        echo "Example:"
+        echo "        $0 $X86_TARGET"
+        echo "        $0 $STM32_TARGET"
+        exit 1
+fi
+
+TARGET=$1
+
+if [ "$TARGET" = "$X86_TARGET" ] ; then
+        cp prj_qemu_x86_nommu.conf prj.conf
+        rm -fr build && mkdir build && cd build
+        cmake -GNinja -DBOARD=qemu_x86_nommu -DWAMR_BUILD_TARGET=X86_32 ..
+        ninja
+        ninja run
+elif [ "$TARGET" = "$STM32_TARGET" ] ; then
+        cp prj_nucleo767zi.conf prj.conf
+        rm -fr build && mkdir build && cd build
+        cmake -GNinja -DBOARD=nucleo_f767zi -DWAMR_BUILD_TARGET=THUMBV7 ..
+        ninja
+        ninja flash
+else
+        echo "unsupported target: $TARGET"
+        exit 1
+fi

product-mini/platforms/zephyr/simple/prj.conf

@@ -1,5 +0,0 @@
-# set CONFIG_ARM_MPU=y if run in ARM's board
-# CONFIG_ARM_MPU is not set
-CONFIG_STACK_SENTINEL=y
-CONFIG_PRINTK=y
-CONFIG_LOG=y

product-mini/platforms/zephyr/simple/prj_nucleo767zi.conf

@@ -0,0 +1,7 @@
+# Copyright (C) 2019 Intel Corporation.  All rights reserved.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+CONFIG_ARM_MPU=y
+CONFIG_STACK_SENTINEL=y
+CONFIG_PRINTK=y
+CONFIG_LOG=y

product-mini/platforms/zephyr/simple/prj_qemu_x86_nommu.conf

@@ -0,0 +1,6 @@
+# Copyright (C) 2019 Intel Corporation.  All rights reserved.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+CONFIG_STACK_SENTINEL=y
+CONFIG_PRINTK=y
+CONFIG_LOG=y