Commit Graph

40 Commits

Author SHA1 Message Date
Wenyong Huang
a0e0a5fa0e
Fix fast jit issues and clear compile warnings (#1228)
Fix i8 bool result misused as i32 reg to compare with i32 0
Fix wasm_runtime_malloc 0 size memory warning
Fix codegen i64 ROTL translation issue
Refine rotate shift operations
Clear compilation warnings of codegen
2022-06-16 09:55:59 +08:00
Wenyong Huang
0ab070af96
Fix fast jit issues (#1223)
Fix br if not clear_value issue
Fix i64.DIV/REM issue: i64 result rax/rdx may be overwritten by following i32 load eax/edx
2022-06-14 07:28:53 +08:00
liang.he
b84f11724b
Avoid modify src reg firstly when src reg and dst reg are the same (#1220) 2022-06-10 15:33:16 +08:00
liang.he
25b48bce35
Refactor opcode inn.trunc_fmm_sx and inn.trunc_fmm_sx_sat (#1215) 2022-06-09 20:33:37 +08:00
liang.he
50982dd145
Implement opcode memory.size (#1217) 2022-06-09 12:10:39 +08:00
liang.he
5e84cf8826
Implement opcode f32.copysign and f64.copysign (#1216)
Implement opcode f32.copysign and f64.copysign for fast jit
2022-06-09 11:12:47 +08:00
Wenyong Huang
d11bfdf0e3
Fix fast jit int rem_s and const shl issues (#1213)
int rem_s -1 should return 0
int32 lhs << int32 rhs may cause sanitizer check failure
fix codegen I8TOI64, I16TOI64, I64TOI8, I64TOI16
implement codegen neg operations
2022-06-09 08:54:14 +08:00
Wenyong Huang
ab2e959616
Fix fast jit issues (#1208)
Move jit spill cache to the end of interp frame to reduce footprint
Fix codegen compare float issue: should not overwritten the source registers
Fix float to int conversion check integer overflow issue
Unify the float compare
Fix get_global issue
2022-06-07 15:49:52 +08:00
Wenyong Huang
5e9f08fb68
Refactor emitting callnative/callbc IRs (#1206)
And remove clear_values for opcode br_if as the jit registers
can be used in the same basic block.
2022-06-06 11:11:02 +08:00
liang.he
95eb0e3363
Use CALLNATIVE to replace generate instructions (#1205)
can't handle NaN simply

pass f32.wast and f64.wast
2022-06-03 10:34:33 +08:00
liang.he
b3a27e7257
Fix issues of fnn.cmp (#1204)
- use native functions to do f.eq and f.ne
- only use ZF=0 and CF=0 to do f.lt and f.gt
- only use CF=0 to do f.le and f.ge

could use comiss and setCC to replace comiss and jmpCC

be able to pass f32_cmp and f64_cmp

```
cmp_eq:
  xor     eax, eax
  ucomisd xmm0, xmm1
  mov     edx, 0
  setnp   al
  cmovne  eax, edx
  ret

cmp_ne:
  xor     eax, eax
  ucomisd xmm0, xmm1
  mov edx, 1
  setp al
  cmovne eax, edx
  ret
```
2022-06-03 10:02:51 +08:00
Wenyong Huang
66cd90d847
Fix fast jit issues (#1201) 2022-06-02 16:41:48 +08:00
liang.he
9694ad7890
Implement inn.extend8_s, inn.extend16_s, i64.extend32_s (#1199) 2022-06-01 11:18:22 +08:00
liang.he
c93508939a
Lock register to avoid spilling it out by register allocator (#1188)
In one instruction, if one or multiple operands tending to lock some
hardware registers in IR phase, like EAX, EDX for DIV, ECX for SHIFT,
it leads to two known cases.

case 1: allocate VOID

`SHRU i250,i249,i3`. if pr_3 was allocated to vr_249 first, incoming
allocation of vr_3 leads a spill out of `vr_249` and clear the value
of `vr->hreg` of vr_249. When applying allocation result in FOREACH
in L732, a NULL will be assigned to.

case 2: unexpected spill out

`DIV_U i1,i1,i44`.  if allocation of vr_44 needs to spill out one
hardware register, there is a chance that `hr_4` will be selected.
If it happens, codegen will operate EDX and overwrite vr_44 value.

The reason of how `hr_4` will be spilled out is a hidden bug that
both information of `rc->hreg[]` and `rc->vreg` can be transfered
from one block to the next one. It means even there is no vr binds
to a hr in current block, the hr may still be thought as a busy one
becase of the left infroamtion of previous blocks

Workaround for cases:

- Add `MOV LOCKED_hr LOCKED_hr` just after the instruction. It prevents
  case 1
- Add `MOV LOCKED_hr LOCKED_hr` just before the instruction. It prevents
  case 2
2022-05-31 11:58:02 +08:00
liang.he
8350d9860b
Unify results of SELECTCC (#1197) 2022-05-30 19:44:08 +08:00
Wenyong Huang
9e3c6acb25
Fix fast jit issues (#1193)
And implement several opcodes
2022-05-30 15:27:22 +08:00
liang.he
b01ae11217
Implement float comparison, conversion and numeric opcodes (#1170) 2022-05-24 19:03:46 +08:00
Wenyong Huang
e675564381
Fix fast jit issues (#1169)
Implement bitwise 64-bit operations in codegen
Fix and refine shift IRs
Zero local variables
Remove ref-type/bulk-memory macros
Implement set aux stack
Refine clear mem registers
2022-05-16 15:17:48 +08:00
liang.he
eec5450d26
Implement fast jit float/double load/store opcodes translation (#1165) 2022-05-10 17:23:53 +08:00
Wenyong Huang
4135622008
Fix fast jit several issues (#1163) 2022-05-10 15:22:43 +08:00
liang.he
dd966977a5
Implement JIT IR translation for opcode call_indirect (#1138) 2022-05-06 15:31:21 +08:00
liang.he
87b259a40a
Implement opcode memory.grow and fix zydis compile error (#1123) 2022-04-27 20:02:38 +08:00
liang.he
26c4a7ca33
Only handle one const case in DEF_UNI_INT_CONST_OPS (#1122)
`DEF_UNI_INT_CONST_OPS` handle the case of both consts
2022-04-26 15:59:15 +08:00
liang.he
0377aec027
Emit JIT IRs for wasm opcode ROTL and ROTR (#1114) 2022-04-24 13:50:27 +08:00
liang.he
ab5eaef5b8
Implement I64_EXTEND_I32 and I32_WRAP_I64 for Fast JIT (#1111) 2022-04-21 18:15:56 +08:00
liang.he
0c2cac4ca2
Emit JIT IR for bitwise opcodes (#1101) 2022-04-21 17:48:24 +08:00
liang.he
94d6da28b7
Emit JIT IR for wasm opcode SHL/SHRU/SHRS (#1097) 2022-04-19 16:24:37 +08:00
liang.he
166f12fef1
Implement JIT IR for integer load/store opcodes (#1087) 2022-04-18 17:22:55 +08:00
Wenyong Huang
5f0fab03a5
Implement i32/i64 div and rem opcodes translation (#1091) 2022-04-18 11:38:10 +08:00
liang.he
f1f674bc8d
Emit JIT IRs for get/set wasm globals (#1085)
WASM_OP_SET_GLOBAL_AUX_STACK is unsupported currently
2022-04-14 14:07:37 +08:00
liang.he
8ef253a19c
Emit JIT IR for integer comparison (#1086) 2022-04-13 13:43:45 +08:00
Wenyong Huang
27446e4b14
Implement load fixed virtual regs (#1083) 2022-04-12 14:54:38 +08:00
Wenyong Huang
d4fe9fcbdc
Add pointer reg and LDPTR/STPTR to refine the code (#1079)
And define the fixed virtual registers, create them at the beginning.
2022-04-12 09:01:08 +08:00
Wenyong Huang
3b7bc63274
Implement op_call for fast-jit (#1075)
Translate WASM_OP_CALL into JIT IR in the frontend, and translate
JIT_OP_CALLBC and JIT_OP_CALLNATIVE in the backend.
For calling wasm native API, simply call wasm_interp_call_func_native
to reduce the complexity.
And fix some issues, including wasm loader, frontend, register allocator,
and code gen.
2022-04-10 18:41:23 +08:00
liang.he
4d966d45ee
Fix issues of compiling control related opcodes (#1063) 2022-04-03 20:25:13 +08:00
liang.he
8113536278
Implement IR translation of BR_TABLE (#1064)
And refine IR translation of BR_IF
2022-04-02 14:02:06 +08:00
Wenyong Huang
f7b6cd75c7
Implement part of codegen, add asmjit and zydis (#1050)
Implement part of codegen and fix some frontend issues
Add asmjit to emit native code and add zydis to disassemble native code
Can successfully run some simple cases
2022-03-22 12:22:04 +08:00
liang.he
0f2885cd66
Fix issues of handling op block/if/loop/else (#1049)
Since `basic_block_else` is NULL, it meets a crash if there is a
IF block without a else branch. Like:

``` wat
(func (export "params-id") (param i32) (result i32)
  (i32.const 1)
  (if (param i32) (result i32) (local.get 0)
    (then)
  )
)
```

Consider the ELSE block will be created lazily, focus on
`basic_block_entry" here.
2022-03-21 14:00:58 +08:00
Wenyong Huang
eb518c0423
Refine code, fix some issues and add codegen framework (#1045)
Add more return value checks and set lass error
Implement exception throw and add operand stack overflow check
Remove lower_fe pass
Use cc->cmp_reg for cmp/branch IRs
Fix jit dump issues
Fix some compile warnings
Add part of codegen framework
Remove some unused JIT IRs
2022-03-14 15:32:32 +08:00
Wenyong Huang
24aae4f0d6
Import Fast JIT framework (#1016)
Import Fast JIT framework and translate some opcodes in the frontend.
2022-03-09 12:34:56 +08:00