mirror of
https://github.com/bytecodealliance/wasm-micro-runtime.git
synced 2025-02-06 15:05:19 +00:00
Merge branch 'dev/simd_for_interp' into makslit/local_global
This commit is contained in:
Maks Litskevich
GitHub
commit
2ad362ce6f
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@ -5837,8 +5837,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
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{
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uint32 offset, addr;
|
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offset = read_uint32(frame_ip);
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addr = GET_OPERAND(uint32, I32, 0);
|
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frame_ip += 2;
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addr = POP_I32();
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addr_ret = GET_OFFSET();
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CHECK_MEMORY_OVERFLOW(16);
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PUT_V128_TO_ADDR(frame_lp + addr_ret, LOAD_V128(maddr));
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@ -5932,10 +5931,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
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uint32 offset, addr;
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offset = read_uint32(frame_ip);
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V128 data = POP_V128();
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int32 base = POP_I32();
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offset += base;
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addr = GET_OPERAND(uint32, I32, 0);
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addr = POP_I32();
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CHECK_MEMORY_OVERFLOW(16);
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STORE_V128(maddr, data);
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break;
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@ -6183,7 +6179,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
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}
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case SIMD_i8x16_lt_u:
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{
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SIMD_DOUBLE_OP(simde_wasm_i8x16_lt);
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SIMD_DOUBLE_OP(simde_wasm_u8x16_lt);
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break;
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}
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case SIMD_i8x16_gt_s:
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@ -6193,7 +6189,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
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}
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case SIMD_i8x16_gt_u:
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{
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SIMD_DOUBLE_OP(simde_wasm_i8x16_gt);
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SIMD_DOUBLE_OP(simde_wasm_u8x16_gt);
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break;
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}
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case SIMD_i8x16_le_s:
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@ -6203,7 +6199,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
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}
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case SIMD_i8x16_le_u:
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{
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SIMD_DOUBLE_OP(simde_wasm_i8x16_le);
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SIMD_DOUBLE_OP(simde_wasm_u8x16_le);
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break;
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}
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case SIMD_i8x16_ge_s:
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@ -6213,7 +6209,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
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}
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case SIMD_i8x16_ge_u:
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{
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SIMD_DOUBLE_OP(simde_wasm_i8x16_ge);
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SIMD_DOUBLE_OP(simde_wasm_u8x16_ge);
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break;
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}
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@ -6235,7 +6231,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
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}
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case SIMD_i16x8_lt_u:
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{
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SIMD_DOUBLE_OP(simde_wasm_i16x8_lt);
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SIMD_DOUBLE_OP(simde_wasm_u16x8_lt);
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break;
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}
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case SIMD_i16x8_gt_s:
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@ -6245,7 +6241,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
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}
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case SIMD_i16x8_gt_u:
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{
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SIMD_DOUBLE_OP(simde_wasm_i16x8_gt);
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SIMD_DOUBLE_OP(simde_wasm_u16x8_gt);
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break;
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}
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case SIMD_i16x8_le_s:
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@ -6255,7 +6251,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
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}
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case SIMD_i16x8_le_u:
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{
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SIMD_DOUBLE_OP(simde_wasm_i16x8_le);
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SIMD_DOUBLE_OP(simde_wasm_u16x8_le);
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break;
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}
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case SIMD_i16x8_ge_s:
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@ -6265,7 +6261,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
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}
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case SIMD_i16x8_ge_u:
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{
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SIMD_DOUBLE_OP(simde_wasm_i16x8_ge);
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SIMD_DOUBLE_OP(simde_wasm_u16x8_ge);
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break;
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}
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@ -6287,7 +6283,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
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}
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case SIMD_i32x4_lt_u:
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{
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SIMD_DOUBLE_OP(simde_wasm_i32x4_lt);
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SIMD_DOUBLE_OP(simde_wasm_u32x4_lt);
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break;
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}
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case SIMD_i32x4_gt_s:
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@ -6297,7 +6293,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
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}
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case SIMD_i32x4_gt_u:
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{
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SIMD_DOUBLE_OP(simde_wasm_i32x4_gt);
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SIMD_DOUBLE_OP(simde_wasm_u32x4_gt);
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break;
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}
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case SIMD_i32x4_le_s:
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@ -6307,7 +6303,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
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}
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case SIMD_i32x4_le_u:
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{
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SIMD_DOUBLE_OP(simde_wasm_i32x4_le);
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SIMD_DOUBLE_OP(simde_wasm_u32x4_le);
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break;
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}
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case SIMD_i32x4_ge_s:
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@ -6317,7 +6313,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
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}
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case SIMD_i32x4_ge_u:
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{
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SIMD_DOUBLE_OP(simde_wasm_i32x4_ge);
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SIMD_DOUBLE_OP(simde_wasm_u32x4_ge);
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break;
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}
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@ -6356,32 +6352,32 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
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/* f64x2 comparison operations */
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case SIMD_f64x2_eq:
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{
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SIMD_DOUBLE_OP(simde_wasm_f32x4_eq);
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SIMD_DOUBLE_OP(simde_wasm_f64x2_eq);
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break;
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}
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case SIMD_f64x2_ne:
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{
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SIMD_DOUBLE_OP(simde_wasm_f32x4_ne);
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SIMD_DOUBLE_OP(simde_wasm_f64x2_ne);
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break;
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}
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case SIMD_f64x2_lt:
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{
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SIMD_DOUBLE_OP(simde_wasm_f32x4_lt);
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SIMD_DOUBLE_OP(simde_wasm_f64x2_lt);
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break;
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}
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case SIMD_f64x2_gt:
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{
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SIMD_DOUBLE_OP(simde_wasm_f32x4_gt);
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SIMD_DOUBLE_OP(simde_wasm_f64x2_gt);
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break;
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}
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case SIMD_f64x2_le:
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{
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SIMD_DOUBLE_OP(simde_wasm_f32x4_le);
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SIMD_DOUBLE_OP(simde_wasm_f64x2_le);
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break;
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}
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case SIMD_f64x2_ge:
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{
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SIMD_DOUBLE_OP(simde_wasm_f32x4_ge);
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SIMD_DOUBLE_OP(simde_wasm_f64x2_ge);
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break;
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}
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@ -6464,7 +6460,6 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
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#define SIMD_LOAD_LANE_COMMON(vec, register, lane, width) \
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do { \
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addr = GET_OPERAND(uint32, I32, 0); \
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addr_ret = GET_OFFSET(); \
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CHECK_MEMORY_OVERFLOW(width / 8); \
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if (width == 64) { \
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@ -6481,8 +6476,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
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uint32 offset, addr; \
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offset = read_uint32(frame_ip); \
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V128 vec = POP_V128(); \
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int32 base = POP_I32(); \
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offset += base; \
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addr = POP_I32(); \
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int lane = *frame_ip++; \
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SIMD_LOAD_LANE_COMMON(vec, register, lane, width); \
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} while (0)
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@ -6512,11 +6506,8 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
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uint32 offset, addr; \
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offset = read_uint32(frame_ip); \
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V128 vec = POP_V128(); \
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int32 base = POP_I32(); \
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offset += base; \
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addr = POP_I32(); \
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int lane = *frame_ip++; \
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addr = GET_OPERAND(uint32, I32, 0); \
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addr_ret = GET_OFFSET(); \
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CHECK_MEMORY_OVERFLOW(width / 8); \
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if (width == 64) { \
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STORE_I64(maddr, vec.register[lane]); \
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@ -6553,8 +6544,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
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do { \
|
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uint32 offset, addr; \
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offset = read_uint32(frame_ip); \
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int32 base = POP_I32(); \
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offset += base; \
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addr = POP_I32(); \
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int32 lane = 0; \
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V128 vec = { 0 }; \
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SIMD_LOAD_LANE_COMMON(vec, register, lane, width); \
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@ -6642,7 +6632,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
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}
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case SIMD_i8x16_narrow_i16x8_u:
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{
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SIMD_DOUBLE_OP(simde_wasm_i8x16_narrow_i16x8);
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SIMD_DOUBLE_OP(simde_wasm_u8x16_narrow_i16x8);
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||||
break;
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||||
}
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case SIMD_f32x4_ceil:
|
||||
|
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@ -6692,7 +6682,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
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}
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case SIMD_i8x16_shr_u:
|
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{
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SIMD_LANE_SHIFT(simde_wasm_i8x16_shr);
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SIMD_LANE_SHIFT(simde_wasm_u8x16_shr);
|
||||
break;
|
||||
}
|
||||
case SIMD_i8x16_add:
|
||||
|
|
@ -6707,7 +6697,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
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}
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case SIMD_i8x16_add_sat_u:
|
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{
|
||||
SIMD_DOUBLE_OP(simde_wasm_i8x16_add_sat);
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SIMD_DOUBLE_OP(simde_wasm_u8x16_add_sat);
|
||||
break;
|
||||
}
|
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case SIMD_i8x16_sub:
|
||||
|
|
@ -6722,7 +6712,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
|
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}
|
||||
case SIMD_i8x16_sub_sat_u:
|
||||
{
|
||||
SIMD_DOUBLE_OP(simde_wasm_i8x16_sub_sat);
|
||||
SIMD_DOUBLE_OP(simde_wasm_u8x16_sub_sat);
|
||||
break;
|
||||
}
|
||||
case SIMD_f64x2_ceil:
|
||||
|
|
@ -6742,7 +6732,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
|
|||
}
|
||||
case SIMD_i8x16_min_u:
|
||||
{
|
||||
SIMD_DOUBLE_OP(simde_wasm_i8x16_min);
|
||||
SIMD_DOUBLE_OP(simde_wasm_u8x16_min);
|
||||
break;
|
||||
}
|
||||
case SIMD_i8x16_max_s:
|
||||
|
|
@ -6752,7 +6742,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
|
|||
}
|
||||
case SIMD_i8x16_max_u:
|
||||
{
|
||||
SIMD_DOUBLE_OP(simde_wasm_i8x16_max);
|
||||
SIMD_DOUBLE_OP(simde_wasm_u8x16_max);
|
||||
break;
|
||||
}
|
||||
case SIMD_f64x2_trunc:
|
||||
|
|
@ -6772,7 +6762,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
|
|||
}
|
||||
case SIMD_i16x8_extadd_pairwise_i8x16_u:
|
||||
{
|
||||
SIMD_SINGLE_OP(simde_wasm_i16x8_extadd_pairwise_i8x16);
|
||||
SIMD_SINGLE_OP(simde_wasm_u16x8_extadd_pairwise_u8x16);
|
||||
break;
|
||||
}
|
||||
case SIMD_i32x4_extadd_pairwise_i16x8_s:
|
||||
|
|
@ -6782,7 +6772,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
|
|||
}
|
||||
case SIMD_i32x4_extadd_pairwise_i16x8_u:
|
||||
{
|
||||
SIMD_SINGLE_OP(simde_wasm_i32x4_extadd_pairwise_i16x8);
|
||||
SIMD_SINGLE_OP(simde_wasm_u32x4_extadd_pairwise_u16x8);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -6831,7 +6821,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
|
|||
}
|
||||
case SIMD_i16x8_narrow_i32x4_u:
|
||||
{
|
||||
SIMD_DOUBLE_OP(simde_wasm_i16x8_narrow_i32x4);
|
||||
SIMD_DOUBLE_OP(simde_wasm_u16x8_narrow_i32x4);
|
||||
break;
|
||||
}
|
||||
case SIMD_i16x8_extend_low_i8x16_s:
|
||||
|
|
@ -6846,12 +6836,12 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
|
|||
}
|
||||
case SIMD_i16x8_extend_low_i8x16_u:
|
||||
{
|
||||
SIMD_SINGLE_OP(simde_wasm_i16x8_extend_low_i8x16);
|
||||
SIMD_SINGLE_OP(simde_wasm_u16x8_extend_low_u8x16);
|
||||
break;
|
||||
}
|
||||
case SIMD_i16x8_extend_high_i8x16_u:
|
||||
{
|
||||
SIMD_SINGLE_OP(simde_wasm_i16x8_extend_high_i8x16);
|
||||
SIMD_SINGLE_OP(simde_wasm_u16x8_extend_high_u8x16);
|
||||
break;
|
||||
}
|
||||
case SIMD_i16x8_shl:
|
||||
|
|
@ -6866,7 +6856,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
|
|||
}
|
||||
case SIMD_i16x8_shr_u:
|
||||
{
|
||||
SIMD_LANE_SHIFT(simde_wasm_i16x8_shr);
|
||||
SIMD_LANE_SHIFT(simde_wasm_u16x8_shr);
|
||||
break;
|
||||
}
|
||||
case SIMD_i16x8_add:
|
||||
|
|
@ -6881,7 +6871,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
|
|||
}
|
||||
case SIMD_i16x8_add_sat_u:
|
||||
{
|
||||
SIMD_DOUBLE_OP(simde_wasm_i16x8_add_sat);
|
||||
SIMD_DOUBLE_OP(simde_wasm_u16x8_add_sat);
|
||||
break;
|
||||
}
|
||||
case SIMD_i16x8_sub:
|
||||
|
|
@ -6896,7 +6886,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
|
|||
}
|
||||
case SIMD_i16x8_sub_sat_u:
|
||||
{
|
||||
SIMD_DOUBLE_OP(simde_wasm_i16x8_sub_sat);
|
||||
SIMD_DOUBLE_OP(simde_wasm_u16x8_sub_sat);
|
||||
break;
|
||||
}
|
||||
case SIMD_f64x2_nearest:
|
||||
|
|
@ -6916,7 +6906,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
|
|||
}
|
||||
case SIMD_i16x8_min_u:
|
||||
{
|
||||
SIMD_DOUBLE_OP(simde_wasm_i16x8_min);
|
||||
SIMD_DOUBLE_OP(simde_wasm_u16x8_min);
|
||||
break;
|
||||
}
|
||||
case SIMD_i16x8_max_s:
|
||||
|
|
@ -6926,7 +6916,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
|
|||
}
|
||||
case SIMD_i16x8_max_u:
|
||||
{
|
||||
SIMD_DOUBLE_OP(simde_wasm_i16x8_max);
|
||||
SIMD_DOUBLE_OP(simde_wasm_u16x8_max);
|
||||
break;
|
||||
}
|
||||
case SIMD_i16x8_avgr_u:
|
||||
|
|
@ -6946,12 +6936,12 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
|
|||
}
|
||||
case SIMD_i16x8_extmul_low_i8x16_u:
|
||||
{
|
||||
SIMD_DOUBLE_OP(simde_wasm_i16x8_extmul_low_i8x16);
|
||||
SIMD_DOUBLE_OP(simde_wasm_u16x8_extmul_low_u8x16);
|
||||
break;
|
||||
}
|
||||
case SIMD_i16x8_extmul_high_i8x16_u:
|
||||
{
|
||||
SIMD_DOUBLE_OP(simde_wasm_i16x8_extmul_high_i8x16);
|
||||
SIMD_DOUBLE_OP(simde_wasm_u16x8_extmul_high_u8x16);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -7000,12 +6990,12 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
|
|||
}
|
||||
case SIMD_i32x4_extend_low_i16x8_u:
|
||||
{
|
||||
SIMD_SINGLE_OP(simde_wasm_i32x4_extend_low_i16x8);
|
||||
SIMD_SINGLE_OP(simde_wasm_u32x4_extend_low_u16x8);
|
||||
break;
|
||||
}
|
||||
case SIMD_i32x4_extend_high_i16x8_u:
|
||||
{
|
||||
SIMD_SINGLE_OP(simde_wasm_i32x4_extend_high_i16x8);
|
||||
SIMD_SINGLE_OP(simde_wasm_u32x4_extend_high_u16x8);
|
||||
break;
|
||||
}
|
||||
case SIMD_i32x4_shl:
|
||||
|
|
@ -7020,7 +7010,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
|
|||
}
|
||||
case SIMD_i32x4_shr_u:
|
||||
{
|
||||
SIMD_LANE_SHIFT(simde_wasm_i32x4_shr);
|
||||
SIMD_LANE_SHIFT(simde_wasm_u32x4_shr);
|
||||
break;
|
||||
}
|
||||
case SIMD_i32x4_add:
|
||||
|
|
@ -7045,7 +7035,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
|
|||
}
|
||||
case SIMD_i32x4_min_u:
|
||||
{
|
||||
SIMD_DOUBLE_OP(simde_wasm_i32x4_min);
|
||||
SIMD_DOUBLE_OP(simde_wasm_u32x4_min);
|
||||
break;
|
||||
}
|
||||
case SIMD_i32x4_max_s:
|
||||
|
|
@ -7055,7 +7045,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
|
|||
}
|
||||
case SIMD_i32x4_max_u:
|
||||
{
|
||||
SIMD_DOUBLE_OP(simde_wasm_i32x4_max);
|
||||
SIMD_DOUBLE_OP(simde_wasm_u32x4_max);
|
||||
break;
|
||||
}
|
||||
case SIMD_i32x4_dot_i16x8_s:
|
||||
|
|
@ -7075,12 +7065,12 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
|
|||
}
|
||||
case SIMD_i32x4_extmul_low_i16x8_u:
|
||||
{
|
||||
SIMD_DOUBLE_OP(simde_wasm_i32x4_extmul_low_i16x8);
|
||||
SIMD_DOUBLE_OP(simde_wasm_u32x4_extmul_low_u16x8);
|
||||
break;
|
||||
}
|
||||
case SIMD_i32x4_extmul_high_i16x8_u:
|
||||
{
|
||||
SIMD_DOUBLE_OP(simde_wasm_i32x4_extmul_high_i16x8);
|
||||
SIMD_DOUBLE_OP(simde_wasm_u32x4_extmul_high_u16x8);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -7129,12 +7119,12 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
|
|||
}
|
||||
case SIMD_i64x2_extend_low_i32x4_u:
|
||||
{
|
||||
SIMD_SINGLE_OP(simde_wasm_i64x2_extend_low_i32x4);
|
||||
SIMD_SINGLE_OP(simde_wasm_u64x2_extend_low_u32x4);
|
||||
break;
|
||||
}
|
||||
case SIMD_i64x2_extend_high_i32x4_u:
|
||||
{
|
||||
SIMD_SINGLE_OP(simde_wasm_i64x2_extend_high_i32x4);
|
||||
SIMD_SINGLE_OP(simde_wasm_u64x2_extend_high_u32x4);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -7151,7 +7141,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
|
|||
}
|
||||
case SIMD_i64x2_shr_u:
|
||||
{
|
||||
SIMD_LANE_SHIFT(simde_wasm_i64x2_shr);
|
||||
SIMD_LANE_SHIFT(simde_wasm_u64x2_shr);
|
||||
break;
|
||||
}
|
||||
case SIMD_i64x2_add:
|
||||
|
|
@ -7211,12 +7201,12 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
|
|||
}
|
||||
case SIMD_i64x2_extmul_low_i32x4_u:
|
||||
{
|
||||
SIMD_DOUBLE_OP(simde_wasm_i64x2_extmul_low_i32x4);
|
||||
SIMD_DOUBLE_OP(simde_wasm_u64x2_extmul_low_u32x4);
|
||||
break;
|
||||
}
|
||||
case SIMD_i64x2_extmul_high_i32x4_u:
|
||||
{
|
||||
SIMD_DOUBLE_OP(simde_wasm_i64x2_extmul_high_i32x4);
|
||||
SIMD_DOUBLE_OP(simde_wasm_u64x2_extmul_high_u32x4);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -7342,7 +7332,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
|
|||
}
|
||||
case SIMD_i32x4_trunc_sat_f32x4_u:
|
||||
{
|
||||
SIMD_SINGLE_OP(simde_wasm_i32x4_trunc_sat_f32x4);
|
||||
SIMD_SINGLE_OP(simde_wasm_u32x4_trunc_sat_f32x4);
|
||||
break;
|
||||
}
|
||||
case SIMD_f32x4_convert_i32x4_s:
|
||||
|
|
@ -7352,7 +7342,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
|
|||
}
|
||||
case SIMD_f32x4_convert_i32x4_u:
|
||||
{
|
||||
SIMD_SINGLE_OP(simde_wasm_f32x4_convert_i32x4);
|
||||
SIMD_SINGLE_OP(simde_wasm_f32x4_convert_u32x4);
|
||||
break;
|
||||
}
|
||||
case SIMD_i32x4_trunc_sat_f64x2_s_zero:
|
||||
|
|
@ -7362,7 +7352,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
|
|||
}
|
||||
case SIMD_i32x4_trunc_sat_f64x2_u_zero:
|
||||
{
|
||||
SIMD_SINGLE_OP(simde_wasm_i32x4_trunc_sat_f64x2_zero);
|
||||
SIMD_SINGLE_OP(simde_wasm_u32x4_trunc_sat_f64x2_zero);
|
||||
break;
|
||||
}
|
||||
case SIMD_f64x2_convert_low_i32x4_s:
|
||||
|
|
@ -7372,7 +7362,7 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
|
|||
}
|
||||
case SIMD_f64x2_convert_low_i32x4_u:
|
||||
{
|
||||
SIMD_SINGLE_OP(simde_wasm_f64x2_convert_low_i32x4);
|
||||
SIMD_SINGLE_OP(simde_wasm_f64x2_convert_low_u32x4);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -15484,10 +15484,6 @@ re_scan:
|
|||
|
||||
read_leb_mem_offset(p, p_end, mem_offset); /* offset */
|
||||
|
||||
#if WASM_ENABLE_FAST_INTERP != 0
|
||||
emit_uint32(loader_ctx, mem_offset);
|
||||
#endif
|
||||
|
||||
CHECK_BUF(p, p_end, 1);
|
||||
lane = read_uint8(p);
|
||||
if (!check_simd_access_lane(opcode1, lane, error_buf,
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user