Commit Graph

800 Commits

Author SHA1 Message Date
liang.he
a9658c245f
Implement reference-types opcodes for fast jit (#1249) 2022-06-29 11:11:13 +08:00
Wenyong Huang
1a826f39a2 Merge main into dev/fast_jit 2022-06-28 23:58:18 +08:00
Wenyong Huang
625d59191d
Update spec cases to latest version (#1253)
Update spec cases of mvp/threads to latest version, update wabt
to 1.0.29. And enhance the wasm loader.
2022-06-28 16:05:16 +08:00
Wenyong Huang
5e238322c2
Enable aot compiler with llvm-14/15 (#1252)
Enable aot compiler and jit based on llvm-14.0 and llvm-15.0git,
replace LLVMBuildLoad/LLVMBuildInBoundsGEP/LLVMBuildCall with
LLVMBuildLoad2/LLVMBuildInBoundsGEP2/LLVMBuildCall2, and pass
them with related types, so as to meet the requirements of opaque
pointers.

And fix several compilation errors for llvm-14.0/15.0git.

Most spec cases and standalone cases are tested.
2022-06-28 14:53:01 +08:00
Cengizhan Pasaoglu
2746d29751
Make robust on choosing target assumption for X86_32 support (#1241)
When WAMR_BUILD_TARGET isn't set, choosing right target is decided
by checking `CMAKE_SIZEOF_VOID_P` variable. However, choosing `X86_32`
target is not doing specifically checking size of void pointer. It is kind
a fallback target for others.

This patch explicitly checks the size of void pointer before setting the target
to `X86_32` to fix the issue.
2022-06-27 20:30:31 +08:00
YAMAMOTO Takashi
eb3cdaaf32
Fix macro redifinition warning for NuttX (#1250)
Fix the following warning introduced by the recent change.

```
In file included from wamr/core/iwasm/libraries/libc-wasi/sandboxed-system-primitives/src/locking.h:17,
                 from wamr/core/iwasm/libraries/libc-wasi/sandboxed-system-primitives/src/posix.h:18,
                 from wamr/core/iwasm/aot/../common/wasm_runtime_common.h:18,
                 from wamr/core/iwasm/aot/aot_runtime.h:10,
                 from wamr/core/iwasm/aot/aot_loader.c:6:
wamr/core/iwasm/libraries/libc-wasi/sandboxed-system-primitives/src/ssp_config.h:55: error: "CONFIG_HAS_ISATTY" redefined [-Werror]
 #define CONFIG_HAS_ISATTY 1

In file included from wamr/core/shared/utils/../platform/include/platform_common.h:13,
                 from wamr/core/shared/utils/bh_platform.h:9,
                 from wamr/core/iwasm/aot/aot_runtime.h:9,
                 from wamr/core/iwasm/aot/aot_loader.c:6:
wamr/core/shared/platform/nuttx/platform_internal.h:75: note: this is the location of the previous definition
 #define CONFIG_HAS_ISATTY 0
```
2022-06-26 10:06:34 +08:00
Wenyong Huang
114bf9408b
Fix get invokeNative float ret value issue with clang compiler (#1248)
When using clang compiler, the f32/f64 return value might be
invalid when calling invokeNative asm code. Declare the return
type of invokeNative as void, and set volatile for the converted
function pointers to resolve the issue.
2022-06-26 09:33:54 +08:00
Xu Jun
471cac4719
Enable dump call stack to a buffer (#1244)
Enable dump call stack to a buffer, use API
`wasm_runtime_get_call_stack_buf_size` to get the required buffer size
and use API
`wasm_runtime_dump_call_stack_to_buf` to dump call stack to a buffer
2022-06-25 21:38:43 +08:00
liang.he
6e4b2dbc76
Implement bulk memory opcodes (#1245) 2022-06-24 16:00:09 +08:00
Wenyong Huang
8ee2e0a22b Merge main into dev/fast_jit 2022-06-20 21:55:42 +08:00
Xu Jun
53b775aa4b
Support integrate 3rd-party toolchains into wamrc (#1237)
Support integrating 3rd-party toolchain llc compiler or asm compiler
into wamrc by setting environment variable WAMRC_LLC_COMPILER
or WAMRC_ASM_COMPILER, wamrc will use these tools to generate
object file from LLVM IR firstly, and then refactor the object file into
aot file.
2022-06-20 13:13:41 +08:00
dongsheng28849455
bc6eda2803
Set nuttx isatty definition according to CONFIG_SERIAL_TERMIOS (#1234)
The isatty definition on nuttx depends on CONFIG_SERIAL_TERMIOS
2022-06-20 11:58:48 +08:00
Xu Jun
d0676930dc
Add arc compiler-rt functions and reloc type for mwdt (#1238)
Add arc compiler-rt functions and reloc type for arc MetaWare
Development Toolkit (mwdt), controlled by macro __CCAC__.
2022-06-20 09:03:31 +08:00
liang.he
f975a987bf
Separate MacOS workflows from the big one (#1236)
Separate MacOS workflows from the big one so as to avoid too much tasks
And optimize the total duration by reducing getting LLVM libraries times
2022-06-17 17:44:20 +08:00
dongsheng28849455
cc942e8c68
Add missing aot relocation symbols for xtensa target (#1235)
Some symbols are missing when loading the xtensa aot file.
2022-06-17 15:11:56 +08:00
Xu Jun
4b38205023
Fix some issues reported by klocwork (#1233)
Change memcpy to bh_memcpy_s and add some asserts to
enhance the security.
2022-06-16 19:50:47 +08:00
Xu Jun
188d5e70e9
Fix typo in wasm_mini_loader.c (#1232) 2022-06-16 12:07:32 +08:00
Wenyong Huang
a0e0a5fa0e
Fix fast jit issues and clear compile warnings (#1228)
Fix i8 bool result misused as i32 reg to compare with i32 0
Fix wasm_runtime_malloc 0 size memory warning
Fix codegen i64 ROTL translation issue
Refine rotate shift operations
Clear compilation warnings of codegen
2022-06-16 09:55:59 +08:00
Xu Jun
b39f4c5c9b
Fix drop opcode issue in fast interpreter (#1231)
Fix fast interpreter issue reported in #1230
2022-06-16 09:51:01 +08:00
Xu Jun
e0a8aa09be
Fix build error when enable custom section without interpreter (#1229) 2022-06-15 18:14:39 +08:00
Xu Jun
1705ae569b
Update spec test script (#1227) 2022-06-15 11:07:39 +08:00
liang.he
5340e3c3de
Fix sanitizer check issue when both def reg and ref reg are the same (#1226)
Fix issue of instruction like MOV i3, i3
2022-06-14 17:13:11 +08:00
liang.he
96fa546cc9
Add a sanitizer to check if there is a definition of vreg before its (#1224) 2022-06-14 10:44:43 +08:00
Wenyong Huang
0ab070af96
Fix fast jit issues (#1223)
Fix br if not clear_value issue
Fix i64.DIV/REM issue: i64 result rax/rdx may be overwritten by following i32 load eax/edx
2022-06-14 07:28:53 +08:00
Xu Jun
77595c9560
Support emit specified custom sections into AoT file (#1207)
And add API to get the content of custom section with
section name for both wasm file and aot file.
2022-06-10 21:51:13 +08:00
liang.he
b84f11724b
Avoid modify src reg firstly when src reg and dst reg are the same (#1220) 2022-06-10 15:33:16 +08:00
liang.he
25b48bce35
Refactor opcode inn.trunc_fmm_sx and inn.trunc_fmm_sx_sat (#1215) 2022-06-09 20:33:37 +08:00
liang.he
50982dd145
Implement opcode memory.size (#1217) 2022-06-09 12:10:39 +08:00
liang.he
5e84cf8826
Implement opcode f32.copysign and f64.copysign (#1216)
Implement opcode f32.copysign and f64.copysign for fast jit
2022-06-09 11:12:47 +08:00
Xu Jun
d404107d85
Fix typo in embed_wamr.md (#1214)
Fix typo in embed_wamr.md reported by #1211
2022-06-09 08:56:45 +08:00
Wenyong Huang
d11bfdf0e3
Fix fast jit int rem_s and const shl issues (#1213)
int rem_s -1 should return 0
int32 lhs << int32 rhs may cause sanitizer check failure
fix codegen I8TOI64, I16TOI64, I64TOI8, I64TOI16
implement codegen neg operations
2022-06-09 08:54:14 +08:00
Xu Jun
93607d0fac
Support print exception info in source debugger (#1212) 2022-06-08 12:17:48 +08:00
Wenyong Huang
ab2e959616
Fix fast jit issues (#1208)
Move jit spill cache to the end of interp frame to reduce footprint
Fix codegen compare float issue: should not overwritten the source registers
Fix float to int conversion check integer overflow issue
Unify the float compare
Fix get_global issue
2022-06-07 15:49:52 +08:00
Wenyong Huang
5e9f08fb68
Refactor emitting callnative/callbc IRs (#1206)
And remove clear_values for opcode br_if as the jit registers
can be used in the same basic block.
2022-06-06 11:11:02 +08:00
liang.he
95eb0e3363
Use CALLNATIVE to replace generate instructions (#1205)
can't handle NaN simply

pass f32.wast and f64.wast
2022-06-03 10:34:33 +08:00
liang.he
b3a27e7257
Fix issues of fnn.cmp (#1204)
- use native functions to do f.eq and f.ne
- only use ZF=0 and CF=0 to do f.lt and f.gt
- only use CF=0 to do f.le and f.ge

could use comiss and setCC to replace comiss and jmpCC

be able to pass f32_cmp and f64_cmp

```
cmp_eq:
  xor     eax, eax
  ucomisd xmm0, xmm1
  mov     edx, 0
  setnp   al
  cmovne  eax, edx
  ret

cmp_ne:
  xor     eax, eax
  ucomisd xmm0, xmm1
  mov edx, 1
  setp al
  cmovne eax, edx
  ret
```
2022-06-03 10:02:51 +08:00
Wenyong Huang
66cd90d847
Fix fast jit issues (#1201) 2022-06-02 16:41:48 +08:00
Wenyong Huang
48cdbee4e0
Update documents (#1203)
Mention the Python binding and Go binding in README.md and
embed_wamr.md.
Fix typo of esp-idf link in build_wamr.md.
2022-06-02 14:33:03 +08:00
YAMAMOTO Takashi
ec299554dd
Remove the code for WASM_ENABLE_GC (#1200)
Remove the code for WASM_ENABLE_GC as it is for a dev branch
2022-06-01 16:46:11 +08:00
Wenyong Huang
5b1dcf2fa2
Implement Go language binding (#1196)
Implement Go binding APIs of runtime, module and instance
Add sample, build scripts and update the document

Co-authored-by: venus-taibai <97893654+venus-taibai@users.noreply.github.com>
2022-06-01 11:35:05 +08:00
liang.he
9694ad7890
Implement inn.extend8_s, inn.extend16_s, i64.extend32_s (#1199) 2022-06-01 11:18:22 +08:00
Wenyong Huang
3d34a91f0b
Implement Python language binding (#1192) (#1195)
Implement the first version of Python language binding

Co-authored-by: liang.he <liang.he@intel.com>
2022-05-31 16:39:46 +08:00
liang.he
c93508939a
Lock register to avoid spilling it out by register allocator (#1188)
In one instruction, if one or multiple operands tending to lock some
hardware registers in IR phase, like EAX, EDX for DIV, ECX for SHIFT,
it leads to two known cases.

case 1: allocate VOID

`SHRU i250,i249,i3`. if pr_3 was allocated to vr_249 first, incoming
allocation of vr_3 leads a spill out of `vr_249` and clear the value
of `vr->hreg` of vr_249. When applying allocation result in FOREACH
in L732, a NULL will be assigned to.

case 2: unexpected spill out

`DIV_U i1,i1,i44`.  if allocation of vr_44 needs to spill out one
hardware register, there is a chance that `hr_4` will be selected.
If it happens, codegen will operate EDX and overwrite vr_44 value.

The reason of how `hr_4` will be spilled out is a hidden bug that
both information of `rc->hreg[]` and `rc->vreg` can be transfered
from one block to the next one. It means even there is no vr binds
to a hr in current block, the hr may still be thought as a busy one
becase of the left infroamtion of previous blocks

Workaround for cases:

- Add `MOV LOCKED_hr LOCKED_hr` just after the instruction. It prevents
  case 1
- Add `MOV LOCKED_hr LOCKED_hr` just before the instruction. It prevents
  case 2
2022-05-31 11:58:02 +08:00
liang.he
8350d9860b
Unify results of SELECTCC (#1197) 2022-05-30 19:44:08 +08:00
Wenyong Huang
9e3c6acb25
Fix fast jit issues (#1193)
And implement several opcodes
2022-05-30 15:27:22 +08:00
YAMAMOTO Takashi
3168ba8dcf
Add comments on trailing uint8[1] members in the "Common" structures (#1189)
Add comments to avoid abusing these members to store extra data.
2022-05-26 11:53:50 +08:00
YAMAMOTO Takashi
3fd763a95c
wasm_export.h: Make RuntimeInitArgs less config dependent (#1190)
This header file is supposed to be used by user code, which is not
a part of WAMR. Usually WAMR configuration is not available there,
remove DEBUG_INTERP macro control in it.
2022-05-25 18:15:51 +08:00
liang.he
b01ae11217
Implement float comparison, conversion and numeric opcodes (#1170) 2022-05-24 19:03:46 +08:00
YAMAMOTO Takashi
2288695a33
product-mini/platforms/nuttx/wamr.mk: Build libc-wasi (#1129) 2022-05-24 16:12:08 +08:00
YAMAMOTO Takashi
da3b519642
core/shared/platform/nuttx: mock several APIs for libc-wasi (#1127) 2022-05-24 12:03:40 +08:00